BLG 231E: Digital Circuits
From The Emerging Circuits and Computation Group at ITU
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Announcements
- Oct. 20th Midterm-1 will be held in rooms 2104 and 5305 between 15:30 - 17:30.
- Oct. 14th The second homework has been posted that is due 4/11/2014 before 13:30.
- Sept. 24th The first homework has been posted that is due 8/10/2014 before 16:30.
- Sept. 7th The class is given in the room 2104 (first floor), EEF.
Syllabus
BLG 231E: Digital Circuits, CRN: 11043, Tuesdays 13:30-16:30, Room: 2104 (EEF), Fall 2014.
Instructor
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Teaching Assistant
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Salih Vehbi Cömert
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Grading
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Textbook
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Reference Books
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Policies
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Weekly Course Plan
Date
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Topic
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Week 1, 9/9/2014 | Introduction |
Week 2, 16/9/2014 | Digital logic fundamentals: gates, combinational circuits, Boolean expressions |
Week 3, 23/9/2014 | Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares" |
Weeks 4, 30/9/2014 | Logic minimization: Karnaugh maps, Quine-McCluskey method |
Weeks 5, 7/10/2014 | HOLIDAY!, no class |
Week 6, 14/10/2014 | Quine-McCluskey method, binary decision diagrams, hazards |
Weeks 7, 21/10/2014 | MIDTERM I |
Week 8, 28/10/2014 | Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.) |
Week 9, 4/11/2014 | Combinational circuit design: arithmetic operations |
Weeks 10, 11/11/2014 | Sequential circuits: latches & flip-flops |
Week 11, 18/11/2014 | Sequential circuits: latches & flip-flops |
Week 12, 25/11/2014 | MIDTERM II |
Weeks 13, 2/12/2014 | Sequential circuit design: state graphs and tables, modules |
Weeks 14, 9/12/2014 | Sequential circuit design: modules, state machines |
Course Materials
Homeworks & Solutions | Exams |
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Homework 1 & Solutions | |
Homework 2 | |