EHB 205E: Introduction to Logic Design

Announcements

Dec. 17th Deadline of the third homework has been extended to 27/12/2019 before 12:30.
Dec. 17th The fourth homework has been posted that is due 27/12/2019 before 12:30.
Dec. 9th The third homework has been posted that is due 24/12/2019 before 12:30.
Nov. 19th To see your grades click here.
Nov. 11th The second homework has been posted that is due 26/11/2019 before 12:30.
Sep. 25th The first homework has been posted that is due 8/10/2019 before 12:30.
Sept. 14th The class is given in the room 4102 (first floor), EEF.

EHB 205E: Introduction to Logic Design, CRN: 11101, Tuesdays 12:30-15:30, Room: 4102 (EEF), Fall 2019.

Instructor	Mustafa Altun Email: altunmus@itu.edu.tr Tel: 02122856635 Office hours: 15:00 – 16:00 on Wednesdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant	Emre Altuner Email: altuner16@itu.edu.tr Room: 3107 EEF
Grading	Quizzes: 10% 2 pop-up quizzes (5% each) - no prior announcement of quiz dates and times Homeworks: 10% 4 homeworks (2.5% each) Midterm Exams: 40% 2 midterms (20% each) during the lecture time that will on 22/10/2019 and 3/12/2019. Final Exam: 40%
Textbook	Wakerly, J. F. (20XX). Digital Design Principles & Practices. Prentice Hall.
Reference Books	Roth Jr, C., & Kinney, L. (20XX). Fundamentals of logic design. Cengage Learning. Mano, M. M., & Kime, C. R. (20XX). Logic and Computer Design Fundamentals. Prentice Hall.
Policies	Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date. Exams are in closed-notes and closed-books format. To be eligible of taking the final exam, you should take both midterms and your midterm average should be at least 25 (out of 100). To pass the course, you should have total of at least 30 (out of 100).

Date	Topic
Week 1, 17/9/2019	Introduction
Week 2, 24/9/2019	Digital logic fundamentals: gates, combinational circuits, Boolean expressions
Week 3, 1/10/2019	Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
Weeks 4, 8/10/2019	Logic minimization: Karnaugh maps, Quine-McCluskey method
Weeks 5, 15/10/2019	Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
Week 6, 22/10/2019	MIDTERM I
Weeks 7, 29/10/2019	HOLIDAY, no class
Week 8, 5/11/2019	HOLIDAY, no class
Week 9, 12/11/2019	Combinational circuit design: implementing Boolean and arithmetic operations
Weeks 10, 19/11/2019	Area-Delay Performance analysis of combinational circuits
Week 11, 26/11/2019	Sequential circuits: latches & flip-flops
Week 12, 3/12/2019	MIDTERM II
Weeks 13, 10/12/2019	Sequential circuit design: state graphs and tables, modules
Weeks 14, 17/12/2019	Sequential circuit design: modules, state machines
Weeks 15, 24/12/2019	Sequential circuit design: modules, state machines

Homeworks & Solutions	Homeworks & Solutions	Quizzes & Solutions	Sample Problems & Solutions	Exams
Homework 1 & Solutions	Homework 3	Quiz 1 & Solutions	Problem Set 1 & Solutions	Midterm 1
Homework 2 & Solutions	Homework 4	Quiz 2 & Solutions	Problem Set 2 & Solutions	Midterm 2