Publications and Presentations
From The Emerging Circuits and Computation Group at ITU
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<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div> | <div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div> | ||
== Computing with Nano-Crossbar Arrays == | == Computing with Nano-Crossbar Arrays == | ||
+ | |||
+ | === Comprehensive === | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
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|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | Ceylan Morgul and [[Mustafa Altun]] | + | | width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''presented at''': |
− | | width=" | + | | width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]] |
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides] | ||
|} | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Onur Tunali and [[Mustafa Altun]] | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | width="550"| | + | | width="550"| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori |
+ | |- valign=top | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]] | ||
+ | |||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | [[Mustafa Altun]], Valentina Ciriani, and Mehdi Tahoori | ||
|- valign="top" | |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
− | + | | [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Lausanne, Switzerland, 2017. | |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]] |
| align="center" width="70" | | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]] |
</span> | </span> | ||
− | <br> [http://www.ecc.itu.edu.tr/images/ | + | <br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides] |
|} | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | width="550"| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori |
− | |- valign= | + | |- valign=top |
− | | ''' | + | | '''presented at''': |
− | + | | [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016. | |
|} | |} | ||
+ | |||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]] |
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]] | ||
+ | </span> | ||
+ | <br> [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]] | ||
|} | |} | ||
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| | | | ||
− | {| | + | {| |
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Ceylan Morgul, Furkan Peker, and [[Mustafa Altun]] |
− | |- valign= | + | |- valign=top |
| '''presented at''': | | '''presented at''': | ||
− | + | | [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016. | |
|} | |} | ||
− | | align=center width="70" | | + | |
+ | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]] |
− | | align="center" width="70" | | + | | align="center" width="70" | |
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]] |
</span> | </span> | ||
− | <br> [http://www.ecc.itu.edu.tr/images/ | + | <br> [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster] |
|} | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
− | |||
| | | | ||
− | {| | + | {| |
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media:Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf | Defect Tolerance in Diode FET and Four-Terminal Switch Based Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | Onur Tunali and [[Mustafa Altun]] | + | | Onur Tunali and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
− | | width="550"| [http:// | + | | width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Boston, USA, 2015. |
|} | |} | ||
− | | align=center width="70" | | + | | align=center width="70" | |
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/ee/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf | Paper]] |
− | | align="center" width="70" | | + | | align="center" width="70" | |
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/f9/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pptx]] |
</span> | </span> | ||
− | <br> [http://www.ecc.itu.edu.tr/images/ | + | <br> [http://www.ecc.itu.edu.tr/images/f/f9/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pptx Slides] |
|} | |} | ||
+ | |||
+ | === Fault/Defect/Variation Tolerance === | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
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|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="624"|[[Media: | + | | width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Furkan Peker and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
| '''accepted in''': | | '''accepted in''': | ||
− | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber= | + | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], DOI:10.1109/TMSCS.2018.2829518, 2018. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]] |
|} | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
| | | | ||
− | {| | + | {| |
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
| Onur Tunali and [[Mustafa Altun]] | | Onur Tunali and [[Mustafa Altun]] | ||
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''presented at''': |
− | | width=" | + | | width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017. |
|} | |} | ||
− | | align=center width="70" | | + | | align=center width="70" | |
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]] |
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides] | ||
|} | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
− | |||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Onur Tunali and [[Mustafa Altun]] |
− | |- valign=top | + | |- valign="top" |
− | | ''' | + | | '''accepted in''': |
− | | width="624" | [http:// | + | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]] |
− | + | ||
|} | |} | ||
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|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | [[Mustafa Altun]] | + | | Onur Tunali and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''appeared in''': |
− | | [http:// | + | | width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]] |
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|} | |} | ||
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{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
− | |||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="624"|[[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Synthesizing Logic with Percolation in Nanoscale Lattices]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | [[Mustafa Altun]] and Marc Riedel |
− | |- valign=top | + | |- valign="top" |
− | | ''' | + | | '''appeared in''': |
− | | [http:// | + | | [http://www.igi-global.com/Bookstore/TitleDetails.aspx?TitleId=1117&DetailsType=Description/ International Journal of Nanotechnology and Molecular Computation], Vol. 3, Issue 2, pp. 12–30, 2011. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/3b/Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Paper]] |
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|} | |} | ||
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|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Nanoscale Digital Computation Through Percolation]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | [[Mustafa Altun]], Marc Riedel, and [http://www.cbs.umn.edu/eeb/contacts/claudia-neuhauser/ Claudia Neuhauser] |
|- valign=top | |- valign=top | ||
| '''presented at''': | | '''presented at''': | ||
− | | [http://www. | + | | [http://www.dac.com IEEE/ACM Design Automation Conference (DAC)], San Francisco, USA, 2009. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0c/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Paper]] |
| align="center" width="70" | | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt]] |
</span> | </span> | ||
− | <br> [http://www.ecc.itu.edu.tr/images/ | + | <br> [http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt Slides] |
|} | |} | ||
+ | |||
+ | === Logic Synthesis === | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
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|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Ceylan Morgul and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''accepted in''': |
− | | width=" | + | | width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], DOI:10.1016/j.vlsi.2018.08.002, 2018. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]] |
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + | ||
|} | |} | ||
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<br> | <br> | ||
[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Paper]] | [[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Paper]] | ||
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|} | |} | ||
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</span> | </span> | ||
<br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt Slides] | <br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt Slides] | ||
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|} | |} | ||
Revision as of 04:38, 20 August 2018
Listed below are the papers, first authored by our group members as an indication that the related research is mainly conducted in our group, and the presentations. All materials are subject to copyrights.
Contents |
Computing with Nano-Crossbar Arrays
Comprehensive
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Fault/Defect/Variation Tolerance
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Logic Synthesis
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National Publications in Turkish
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Reversible Circuit Design
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National Publications in Turkish
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Stochastic and Bit Stream Computing
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National Publications in Turkish
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Approximate Computing
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National Publications in Turkish
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Large-Area Electronics
Organic Transistor Modeling
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Reliability of Electronic Products
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Analog Circuit Design
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National Publications in Turkish
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Discrete Mathematics
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