EHB 205E
From The Emerging Circuits and Computation Group at ITU
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== Announcements == | == Announcements == | ||
− | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> | + | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Jan. 15th</span> Final letter grades have been posted. |
* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Dec. 17th</span> Deadline of [[Media:ehb205e-2019-fall-hw-03.pdf | '''the third homework''']] has been extended to '''27/12/2019''' before 12:30. | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Dec. 17th</span> Deadline of [[Media:ehb205e-2019-fall-hw-03.pdf | '''the third homework''']] has been extended to '''27/12/2019''' before 12:30. | ||
* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Dec. 17th</span> [[Media:ehb205e-2019-fall-hw-04.pdf | '''The fourth homework''']] has been posted that is due '''27/12/2019''' before 12:30. | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Dec. 17th</span> [[Media:ehb205e-2019-fall-hw-04.pdf | '''The fourth homework''']] has been posted that is due '''27/12/2019''' before 12:30. |
Revision as of 12:14, 15 January 2020
Contents |
Announcements
- Jan. 15th Final letter grades have been posted.
- Dec. 17th Deadline of the third homework has been extended to 27/12/2019 before 12:30.
- Dec. 17th The fourth homework has been posted that is due 27/12/2019 before 12:30.
- Dec. 9th The third homework has been posted that is due 24/12/2019 before 12:30.
- Nov. 11th The second homework has been posted that is due 26/11/2019 before 12:30.
- Sep. 25th The first homework has been posted that is due 8/10/2019 before 12:30.
- Sept. 14th The class is given in the room 4102 (first floor), EEF.
Syllabus
EHB 205E: Introduction to Logic Design, CRN: 11101, Tuesdays 12:30-15:30, Room: 4102 (EEF), Fall 2019.
Instructor
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Teaching Assistant
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Emre Altuner
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Grading
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Textbook
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Reference Books
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Policies
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Weekly Course Plan
Date
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Topic
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Week 1, 17/9/2019 | Introduction |
Week 2, 24/9/2019 | Digital logic fundamentals: gates, combinational circuits, Boolean expressions |
Week 3, 1/10/2019 | Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares" |
Weeks 4, 8/10/2019 | Logic minimization: Karnaugh maps, Quine-McCluskey method |
Weeks 5, 15/10/2019 | Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.) |
Week 6, 22/10/2019 | MIDTERM I |
Weeks 7, 29/10/2019 | HOLIDAY, no class |
Week 8, 5/11/2019 | HOLIDAY, no class |
Week 9, 12/11/2019 | Combinational circuit design: implementing Boolean and arithmetic operations |
Weeks 10, 19/11/2019 | Area-Delay Performance analysis of combinational circuits |
Week 11, 26/11/2019 | Sequential circuits: latches & flip-flops |
Week 12, 3/12/2019 | MIDTERM II |
Weeks 13, 10/12/2019 | Sequential circuit design: state graphs and tables, modules |
Weeks 14, 17/12/2019 | Sequential circuit design: modules, state machines |
Weeks 15, 24/12/2019 | Sequential circuit design: modules, state machines |
Course Materials
Homeworks & Solutions | Homeworks & Solutions | Quizzes & Solutions | Sample Problems & Solutions | Exams |
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Homework 1 & Solutions | Homework 3 | Quiz 1 & Solutions | Problem Set 1 & Solutions | Midterm 1 |
Homework 2 & Solutions | Homework 4 | Quiz 2 & Solutions | Problem Set 2 & Solutions | Midterm 2 |