EEF 205E

From The Emerging Circuits and Computation Group at ITU
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{{DISPLAYTITLE: EEF 205E: Introduction to Logic Design}}
 
{{DISPLAYTITLE: EEF 205E: Introduction to Logic Design}}
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== Announcements ==
 
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* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Oct. 4th</span>  The class is given in the room '''6309''' (third floor), EEF.
 
  
 
== Syllabus ==
 
== Syllabus ==
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<div style="font-size: 120%;"> '''EEF 205E: Introduction to Logic Design''', CRN: 15211, Fridays 8:30-11:30, Room: 6309 (EEF), Fall 2023. </div>
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<div style="font-size: 120%;"> '''EEF 205E: Introduction to Logic Design''', CRN: 10843, Fridays 8:30-11:30, Room: 6309 (EEF), Fall 2024. </div>
 
{| border="1" cellspacing="0" cellpadding="5" " width="80%"
 
{| border="1" cellspacing="0" cellpadding="5" " width="80%"
 
   
 
   
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| <div style="font-size: 120%;"> '''Teaching Assistant'''</div>
 
| <div style="font-size: 120%;"> '''Teaching Assistant'''</div>
 
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Emre Altuner
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İsmail Melik Türker
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* Email: altuner16@itu.edu.tr
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* Email: turker16@itu.edu.tr
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* Room: 3107 EEF
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* Room: 1105 EEF
 
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|  <div style="font-size: 120%;"> '''Grading'''</div>
 
|  <div style="font-size: 120%;"> '''Grading'''</div>
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* Midterm Exams: '''50%'''
 
* Midterm Exams: '''50%'''
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** 2 midterms (25% each) during the lecture time that will on '''17/11/2023''' and '''22/12/2023'''.
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** 2 midterms (25% each) during the lecture time that will on '''15/11/2024''' and '''27/12/2024'''.
  
 
* Final Exam: '''40%'''
 
* Final Exam: '''40%'''
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|| <div style="font-size: 120%;"> '''Topic'''</div>
 
|| <div style="font-size: 120%;"> '''Topic'''</div>
 
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|  Week  1, 6/10/2023       || Introduction
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|  Week  1, 4/10/2024       || Introduction
 
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|  Week  2, 13/10/2023       || Digital logic fundamentals: gates, combinational circuits, Boolean expressions
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|  Week  2, 11/10/2024       || Digital logic fundamentals: gates, combinational circuits, Boolean expressions
 
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|  Week  3, 20/10/2023       || Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
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|  Week  3, 18/10/2024       || Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
 
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|  Weeks 4, 27/10/2023 || Logic minimization: Karnaugh maps, Quine-McCluskey method
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|  Weeks 4, 25/10/2024 || Logic minimization: Karnaugh maps, Quine-McCluskey method
 
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|  Weeks 5, 3/11/2023   || Logic minimization: Karnaugh maps, Quine-McCluskey method
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|  Weeks 5, 1/11/2024   || Logic minimization: Karnaugh maps, Quine-McCluskey method
 
|-
 
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|  Week 6, 10/11/2023     || Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
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|  Week 6, 8/11/2024     || Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
 
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|  Weeks 7, 17/11/2023 || MIDTERM I
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|  Weeks 7, 15/11/2024 || MIDTERM I
 
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|  Week  8, 24/11/2023   || Combinational circuit design: implementing Boolean and arithmetic operations
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|  Week  8, 22/11/2024   || HOLIDAY!
 
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|  Week  9, 1/12/2023     || Area-Delay Performance analysis of combinational circuits
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|  Week  9, 29/11/2024     || Combinational circuit design: implementing Boolean and arithmetic operations
 
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|  Weeks 10, 8/12/2023 || Sequential circuits: latches & flip-flops
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|  Weeks 10, 6/12/2024 || Area-Delay Performance analysis of combinational circuits
 
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|  Week  11, 15/12/2023     || Sequential circuit design: state graphs and tables, modules
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|  Week  11, 13/12/2024     || Sequential circuits: latches & flip-flops
 
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|  Week  12, 22/12/2023   || MIDTERM II
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|  Week  12, 20/12/2024   || Sequential circuit design: state graphs and tables, modules
 
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|  Weeks 13, 29/12/2023 || Sequential circuit design: modules, state machines
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|  Weeks 13, 27/12/2024 || MIDTERM II
 
|-
 
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|  Weeks 14, 5/1/2024 || Sequential circuit design: modules, state machines
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|  Weeks 14, 3/1/2025 || Sequential circuit design: modules, state machines
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|-
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|  Weeks 15, 10/1/2025 || Sequential circuit design: modules, state machines
 
|}
 
|}
  
 
== Course Materials ==
 
== Course Materials ==
  
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{| border="1" cellspacing="0" cellpadding="5"
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Shared through Ninova.
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! Homeworks  & Solutions!! Homeworks  & Solutions!! Quizzes & Solutions!! Sample Problems & Solutions !!Exams
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| [[Media:ehb205e-2021-fall-hw-01.pdf | Homework 1]] & [[Media:ehb205e-2021-fall-hw-01-solutions.pdf | Solutions]] || [[Media:ehb205e-2021-fall-hw-03.pdf | Homework 3]] & [[Media:ehb205e-2021-fall-hw-03-solutions.pdf | Solutions]]  ||[[Media:ehb205e-2021-fall-quiz-01.pdf | Quiz 1]] & [[Media:ehb205e-2021-fall-quiz-01-solutions.pdf | Solutions]]  || [[Media:ehb205e-2021-problems-01.pdf | Problem Set 1]] & [[Media:ehb205e-2021-problems-01-solutions.pdf | Solutions]]  || [[Media:ehb205e-2021-fall-midterm-01.pdf | Midterm 1]] & [[Media:ehb205e-2021-fall-midterm-01-solutions.pdf | Solutions]]
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|-
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| [[Media:ehb205e-2021-fall-hw-02.pdf | Homework 2]] || [[Media:ehb205e-2021-fall-hw-04.pdf | Homework 4]] & [[Media:ehb205e-2021-fall-hw-04-solutions.pdf | Solutions]]  || [[Media:ehb205e-2021-fall-quiz-02.pdf | Quiz 2]] & [[Media:ehb205e-2021-fall-quiz-02-solutions.pdf | Solutions]]  || [[Media:ehb205e-2021-problems-02.pdf | Problem Set 2]] & [[Media:ehb205e-2021-problems-02-solutions.pdf | Solutions]]    || [[Media:ehb205e-2021-fall-midterm-02.pdf | Midterm 2]] & [[Media:ehb205e-2021-fall-midterm-02-solutions.pdf | Solutions]]
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|}
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Latest revision as of 14:29, 9 October 2024


[edit] Syllabus

EEF 205E: Introduction to Logic Design, CRN: 10843, Fridays 8:30-11:30, Room: 6309 (EEF), Fall 2024.
Instructor

Mustafa Altun

  • Email: altunmus@itu.edu.tr
  • Tel: 02122856635
  • Office hours: 15:00 – 16:00 on Wednesdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant

İsmail Melik Türker

  • Email: turker16@itu.edu.tr
  • Room: 1105 EEF
Grading
  • Homeworks: 10%
    • 4 homeworks (2.5% each)
  • Midterm Exams: 50%
    • 2 midterms (25% each) during the lecture time that will on 15/11/2024 and 27/12/2024.
  • Final Exam: 40%
Textbook
  • Wakerly, J. F. (20XX). Digital Design Principles & Practices. Prentice Hall.
Reference Books
  • Roth Jr, C., & Kinney, L. (20XX). Fundamentals of logic design. Cengage Learning.
  • Mano, M. M., & Kime, C. R. (20XX). Logic and Computer Design Fundamentals. Prentice Hall.
Policies
  • Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date.
  • Exams are in closed-notes and closed-books format.
  • To be eligible of taking the final or the resit exam, your average, excluding the final, should be at least 40% of the class average.
  • To pass the class, your overall average should be at least 50% of the class average.

[edit] Weekly Course Plan

Date
Topic
Week 1, 4/10/2024 Introduction
Week 2, 11/10/2024 Digital logic fundamentals: gates, combinational circuits, Boolean expressions
Week 3, 18/10/2024 Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
Weeks 4, 25/10/2024 Logic minimization: Karnaugh maps, Quine-McCluskey method
Weeks 5, 1/11/2024 Logic minimization: Karnaugh maps, Quine-McCluskey method
Week 6, 8/11/2024 Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
Weeks 7, 15/11/2024 MIDTERM I
Week 8, 22/11/2024 HOLIDAY!
Week 9, 29/11/2024 Combinational circuit design: implementing Boolean and arithmetic operations
Weeks 10, 6/12/2024 Area-Delay Performance analysis of combinational circuits
Week 11, 13/12/2024 Sequential circuits: latches & flip-flops
Week 12, 20/12/2024 Sequential circuit design: state graphs and tables, modules
Weeks 13, 27/12/2024 MIDTERM II
Weeks 14, 3/1/2025 Sequential circuit design: modules, state machines
Weeks 15, 10/1/2025 Sequential circuit design: modules, state machines

[edit] Course Materials

Shared through Ninova.

Retrieved from "https://www.ecc.itu.edu.tr/index.php?title=EEF_205E&oldid=4569"
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