EHB 322E

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{{DISPLAYTITLE: EHB 322E: Digital Electronic Circuits}}
 
{{DISPLAYTITLE: EHB 322E: Digital Electronic Circuits}}
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== Announcements ==
 
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* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Sept. 19th</span> The class is performed '''physically''' (not virtually) in the room 5302 (third floor), EEF.
 
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* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Sept. 19th</span>  As a simulation tool, Spice is required for homeworks. Among different Spice-based programs, '''LTspice''' is a good and free choice; you can download it by [http://www.linear.com/designtools/software/#LTspice/ '''clicking here'''].
 
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== Syllabus ==
 
== Syllabus ==
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<div style="font-size: 120%;"> '''EHB 322E: Digital Electronic Circuits''', CRN: 12020, Fridays 9:30-12:30, Room: 5302 EEF, Fall 2022. </div>  
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<div style="font-size: 120%;"> '''EHB 322E: Digital Electronic Circuits''', CRN: 22187, Mondays 12:30-15:30, Room: 4102 EEF, Spring 2025. </div>  
 
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{| border="1" cellspacing="0" cellpadding="5" " width="80%"
 
    
 
    
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Didem Erol
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Fatma Betül Fişne
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* Email: erold@itu.edu.tr
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* Email: fisne20@itu.edu.tr
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|  <div style="font-size: 120%;"> '''Grading'''</div>
 
|  <div style="font-size: 120%;"> '''Grading'''</div>
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* Quizzes: '''10%'''
 
* Quizzes: '''10%'''
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** 3 quizzes (10% each) - no prior announcement of quiz dates and times.
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** 2 quizzes (5% each) - no prior announcement of quiz dates and times.
  
 
* Homeworks: '''10%'''
 
* Homeworks: '''10%'''
 
** 2 homeworks (5% each)
 
** 2 homeworks (5% each)
  
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* Midterm Exam: '''20%'''
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* Midterm Exams: '''40%'''
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** 1 midterm during the lecture time that will on '''4/4/2022'''.
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** 2 midterms (20% each) during the lecture time that will on '''7/4/2025''' and '''12/5/2025'''.
  
 
* Final Exam: '''40%'''
 
* Final Exam: '''40%'''
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* Homeworks are due at the beginning of class. Late homeworks will be downgraded by '''20%''' for each day passed the due date.
 
* Homeworks are due at the beginning of class. Late homeworks will be downgraded by '''20%''' for each day passed the due date.
 
* Exams are in '''closed-notes''' and '''closed-books''' format.
 
* Exams are in '''closed-notes''' and '''closed-books''' format.
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* To be eligible of taking the final or the resit exam, your midterm and quiz weighted average should be at least '''25''' (out of 100).
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* To be eligible of taking the final or the resit exam, you should take both midterms and your midterm average should be at least '''25''' (out of 100).
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* The final exam will be '''same''' exam for all sections.
 
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|| <div style="font-size: 120%;"> '''Topic'''</div>
 
|| <div style="font-size: 120%;"> '''Topic'''</div>
 
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|  Week  1, 21/2/2022     || Introduction  
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|  Week  1, 17/2/2025     || Introduction  
 
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|  Week  2, 28/2/2022       || Switching theory & devices for digital circuits and inverters
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|  Week  2, 24/2/2025       || Switching theory & devices for digital circuits and inverters
 
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|  Weeks 3, 7/3/2022  || NMOS/CMOS inverters & their static and dynamic behaviors
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|  Weeks 3, 3/3/2025 || NMOS/CMOS inverters & their static and dynamic behaviors
 
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|  Weeks 4, 14/3/2022   || NMOS/CMOS inverters & their static and dynamic behaviors
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|  Weeks 4, 10/3/2025   || NMOS/CMOS inverters & their static and dynamic behaviors
 
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|  Week 5, 21/3/2022     || Optimization of multiple-stage inverters and buffers  
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|  Week 5, 17/3/2025     || Optimization of multiple-stage inverters and buffers  
 
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|  Weeks 6, 28/3/2022   || Static and complex logic gates and their area-delay-power performance analysis
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|  Weeks 6, 24/3/2025   || Static and complex logic gates and their area-delay-power performance analysis
 
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|  Week 7, 4/4/2022     ||  MIDTERM I
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|  Holiday Week, 31/3/2025     ||  HOLIDAY, no class 
 
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|  Week  8, 11/4/2022   ||  Pass transistor logic with Shannon's expansion and performance analysis
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|  Week  7, 7/4/2025   ||  MIDTERM I 
 
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|  Weeks 9, 18/4/2022 || Dynamic logic gates, synchronization
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|  Weeks 8, 14/4/2025 || Pass transistor logic with Shannon's expansion and performance analysis
 
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|  Week  10, 25/4/2022     ||  Dynamic logic gates performance analysis
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|  Week  9, 21/4/2025     ||  Dynamic logic gates performance analysis
 
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|  Week  11, 2/5/2022     || HOLIDAY, no class  
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|  Week  10, 28/4/2025     ||  Dynamic logic gates, synchronization
 
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|  Weeks 12, 9/5/2022 ||  MIDTERM II
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|  Weeks 11, 5/5/2025 ||  Static and dynamic memory elements: D, SR, and JK flip-flops  
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|  Weeks 13, 16/5/2022 || Static and dynamic memory elements: D, SR, and JK flip-flops  
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|  Week  14, 23/5/2022      || Synchronization and timing analysis of digital circuits having logic and memory elements
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|  Weeks 15, 30/5/2022 || Semiconductor memories and gate arrays: RAM's, ROM's, and flash memories
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== Course Materials ==
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{| border="1" cellspacing="0" cellpadding="5"
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! Quizzes & Solutions!! Homeworks & Solutions!! Midterms & Solutions
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|  Weeks 12, 12/5/2025 || MIDTERM II
 
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|  Week  13, 19/5/2025      || Synchronization and timing analysis of digital circuits having logic and memory elements
 
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|  Weeks 14, 26/5/2025 || Semiconductor memories and gate arrays: RAM's, ROM's, and flash memories
 
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Latest revision as of 08:39, 3 March 2025

[edit] Syllabus

EHB 322E: Digital Electronic Circuits, CRN: 22187, Mondays 12:30-15:30, Room: 4102 EEF, Spring 2025.
Instructor

Mustafa Altun

  • Email: altunmus@itu.edu.tr
  • Tel: 02122856635
  • Office hours: 15:00 – 16:00 on Wednesdays in Room:3005, EEF (or stop by my office any time) or online talk
Teaching Assistant

Fatma Betül Fişne

  • Email: fisne20@itu.edu.tr
Grading
  • Quizzes: 10%
    • 2 quizzes (5% each) - no prior announcement of quiz dates and times.
  • Homeworks: 10%
    • 2 homeworks (5% each)
  • Midterm Exams: 40%
    • 2 midterms (20% each) during the lecture time that will on 7/4/2025 and 12/5/2025.
  • Final Exam: 40%
Reference Books
  • Weste, N., & Harris, D. (20XX). Integrated Circuit Design: International Version: A Circuits and Systems Perspective. Pearson Education,.
  • Rabaey, J. M., Chandrakasan, A. P., & Nikolic, B. (20XX). Digital integrated circuits. Englewood Cliffs: Prentice hall.
  • Uyemura, J. P. (20XX). CMOS logic circuit design. Springer.
  • Kang, S. M., & Leblebici, Y. (20XX). Cmos Digital Integrated Circuits. McGraw-Hill Education.
Policies
  • Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date.
  • Exams are in closed-notes and closed-books format.
  • To be eligible of taking the final or the resit exam, you should take both midterms and your midterm average should be at least 25 (out of 100).
  • The final exam will be same exam for all sections.

[edit] Weekly Course Plan

Date
Topic
Week 1, 17/2/2025 Introduction
Week 2, 24/2/2025 Switching theory & devices for digital circuits and inverters
Weeks 3, 3/3/2025 NMOS/CMOS inverters & their static and dynamic behaviors
Weeks 4, 10/3/2025 NMOS/CMOS inverters & their static and dynamic behaviors
Week 5, 17/3/2025 Optimization of multiple-stage inverters and buffers
Weeks 6, 24/3/2025 Static and complex logic gates and their area-delay-power performance analysis
Holiday Week, 31/3/2025 HOLIDAY, no class
Week 7, 7/4/2025 MIDTERM I
Weeks 8, 14/4/2025 Pass transistor logic with Shannon's expansion and performance analysis
Week 9, 21/4/2025 Dynamic logic gates performance analysis
Week 10, 28/4/2025 Dynamic logic gates, synchronization
Weeks 11, 5/5/2025 Static and dynamic memory elements: D, SR, and JK flip-flops
Weeks 12, 12/5/2025 MIDTERM II
Week 13, 19/5/2025 Synchronization and timing analysis of digital circuits having logic and memory elements
Weeks 14, 26/5/2025 Semiconductor memories and gate arrays: RAM's, ROM's, and flash memories
Retrieved from "https://www.ecc.itu.edu.tr/index.php?title=EHB_322E&oldid=4591"
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