EHB 322E
From The Emerging Circuits and Computation Group at ITU
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== Announcements == | == Announcements == | ||
− | + | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Feb. 28th</span> The class is given in the room 5203 (second floor), EEF. | |
− | + | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Feb. 12st</span> As a simulation tool, Spice is required for homeworks. Among different Spice-based programs, '''LTspice''' is a good and free choice; you can download it by [http://www.linear.com/designtools/software/#LTspice/ '''clicking here''']. | |
− | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Feb. | + | |
− | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Feb. | + | |
== Syllabus == | == Syllabus == | ||
− | <div style="font-size: 120%;"> '''EHB 322E: Digital Electronic Circuits''', CRN: | + | <div style="font-size: 120%;"> '''EHB 322E: Digital Electronic Circuits''', CRN: 22206, Mondays 12:30-15:30, Room: 5203 EEF, Spring 2024. </div> |
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− | + | Yiğit Can Erçetin | |
− | * Email: | + | * Email: ercetin17@itu.edu.tr |
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* Midterm Exams: '''40%''' | * Midterm Exams: '''40%''' | ||
− | ** 2 midterms (20% each) during the lecture time that will on ''' | + | ** 2 midterms (20% each) during the lecture time that will on '''25/3/2024''' and '''29/4/2024'''. |
* Final Exam: '''40%''' | * Final Exam: '''40%''' | ||
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* Exams are in '''closed-notes''' and '''closed-books''' format. | * Exams are in '''closed-notes''' and '''closed-books''' format. | ||
* To be eligible of taking the final or the resit exam, you should take both midterms and your midterm average should be at least '''25''' (out of 100). | * To be eligible of taking the final or the resit exam, you should take both midterms and your midterm average should be at least '''25''' (out of 100). | ||
+ | * The final exam will be '''same''' exam for all sections. | ||
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|| <div style="font-size: 120%;"> '''Topic'''</div> | || <div style="font-size: 120%;"> '''Topic'''</div> | ||
|- | |- | ||
− | | Week 1, | + | | Week 1, 12/2/2024 || Introduction |
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− | | Week 2, | + | | Week 2, 19/2/2024 || Switching theory & devices for digital circuits and inverters |
|- | |- | ||
− | | Weeks 3, | + | | Weeks 3, 26/2/2024 || NMOS/CMOS inverters & their static and dynamic behaviors |
|- | |- | ||
− | | Weeks 4, | + | | Weeks 4, 4/3/2024 || NMOS/CMOS inverters & their static and dynamic behaviors |
|- | |- | ||
− | | Week 5, | + | | Week 5, 11/3/2024 || Optimization of multiple-stage inverters and buffers |
|- | |- | ||
− | | Weeks 6, | + | | Weeks 6, 18/3/2024 || Static and complex logic gates and their area-delay-power performance analysis |
|- | |- | ||
− | | Week 7, | + | | Week 7, 25/3/2024 || MIDTERM I |
|- | |- | ||
− | | Week 8, | + | | Week 8, 1/4/2024 || Pass transistor logic with Shannon's expansion and performance analysis |
|- | |- | ||
− | | Weeks 9, | + | | Weeks 9, 8/4/2024 || HOLIDAY, no class |
|- | |- | ||
− | | Week 10, | + | | Week 10, 15/4/2024 || Dynamic logic gates performance analysis |
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− | | Week 11, | + | | Week 11, 22/4/2024 || Dynamic logic gates, synchronization |
|- | |- | ||
− | | Weeks 12, | + | | Weeks 12, 29/4/2024 || MIDTERM II |
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− | | Weeks 13, | + | | Weeks 13, 6/5/2024 || Static and dynamic memory elements: D, SR, and JK flip-flops |
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− | | Week 14, | + | | Week 14, 13/5/2024 || Synchronization and timing analysis of digital circuits having logic and memory elements |
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− | | Weeks 15, | + | | Weeks 15, 20/5/2024 || Semiconductor memories and gate arrays: RAM's, ROM's, and flash memories |
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== Course Materials == | == Course Materials == | ||
− | + | Shared through Ninova. | |
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Latest revision as of 16:58, 28 February 2024
Contents |
[edit] Announcements
- Feb. 28th The class is given in the room 5203 (second floor), EEF.
- Feb. 12st As a simulation tool, Spice is required for homeworks. Among different Spice-based programs, LTspice is a good and free choice; you can download it by clicking here.
[edit] Syllabus
EHB 322E: Digital Electronic Circuits, CRN: 22206, Mondays 12:30-15:30, Room: 5203 EEF, Spring 2024.
Instructor
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Teaching Assistant
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Yiğit Can Erçetin
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Grading
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Reference Books
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Policies
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[edit] Weekly Course Plan
Date
|
Topic
|
Week 1, 12/2/2024 | Introduction |
Week 2, 19/2/2024 | Switching theory & devices for digital circuits and inverters |
Weeks 3, 26/2/2024 | NMOS/CMOS inverters & their static and dynamic behaviors |
Weeks 4, 4/3/2024 | NMOS/CMOS inverters & their static and dynamic behaviors |
Week 5, 11/3/2024 | Optimization of multiple-stage inverters and buffers |
Weeks 6, 18/3/2024 | Static and complex logic gates and their area-delay-power performance analysis |
Week 7, 25/3/2024 | MIDTERM I |
Week 8, 1/4/2024 | Pass transistor logic with Shannon's expansion and performance analysis |
Weeks 9, 8/4/2024 | HOLIDAY, no class |
Week 10, 15/4/2024 | Dynamic logic gates performance analysis |
Week 11, 22/4/2024 | Dynamic logic gates, synchronization |
Weeks 12, 29/4/2024 | MIDTERM II |
Weeks 13, 6/5/2024 | Static and dynamic memory elements: D, SR, and JK flip-flops |
Week 14, 13/5/2024 | Synchronization and timing analysis of digital circuits having logic and memory elements |
Weeks 15, 20/5/2024 | Semiconductor memories and gate arrays: RAM's, ROM's, and flash memories |
[edit] Course Materials
Shared through Ninova.