Publications and Presentations

From The Emerging Circuits and Computation Group at ITU
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== Emerging Computing Models ==
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Listed below are the papers, '''first authored''' by our group members as an indication that the related research is mainly conducted in our group, and the presentations. Research topics are ordered from newest to oldest as well as by considering their importance. Under each topic, papers are ordered from newest to oldest. All materials are subject to copyrights.
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<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
  
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{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
+
== Computing with Switching Lattices ==
  
 +
=== Technology Development ===
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 
|- valign=top
 
|- valign=top
−
| width="696" |'''Selected Publication'''
+
| width="100" |'''title''':
 +
| width="624"|[[Media:Akkan_EtAl_H_and_Square_Lattice_Technology_Development.pdf | Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches]]
 +
|- valign="top"
 +
| '''authors''':
 +
| width="550"| Nihat Akkan, Serzat Safaltin, Levent Aksoy, Ismail Cevik, Herman Sedef, Csaba Andras Moritz, and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], Vol. 10, Issue 1, pp. 351&ndash;360, 2022.
 
|}
 
|}
−
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
+
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/69/Akkan_EtAl_H_and_Square_Lattice_Technology_Development.pdf]]</span>
 +
<br>
 +
[[Media:Akkan_EtAl_H_and_Square_Lattice_Technology_Development.pdf | Paper]]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | CMOS Implementation of Switching Lattices]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Ismail Cevik, Levent Aksoy, and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/50/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf]]</span>
 +
<br>
 +
[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx Slides]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
 +
|- valign="top"
 +
| '''authors''':
 +
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]</span>
 +
<br>
 +
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
 +
|}
 +
 
 +
=== Logic Synthesis and Fault/Variation Tolerance ===
  
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
|
 
|
 
{|  
 
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
−
| width="524"|[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Logic Synthesis for Switching Lattices]]
+
| width="624"|[[Media:Aksoy_EtAl_Logic_Synthesis_for_Switching_Lattices_under_Delay_Constraint.pdf | Realization of Logic Functions Using Switching Lattices Under a Delay Constraint]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
−
| [[Mustafa Altun]] and [http://cadbio.com/wiki/index.php/Marc_Riedel Marc Riedel]
+
| Levent Aksoy, Nihat Akkan, Herman Sedef, and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
 
| '''appeared&nbsp;in''':
 
| '''appeared&nbsp;in''':
−
| [http://www.computer.org/portal/web/tc IEEE Transactions on Computers], Vol. 61, Issue 11, pp. 1588&ndash;1600, 2012.
+
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 40, Issue 10, pp. 2036&ndash;2048, 2021.
 
|}
 
|}
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
−
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/ca/Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/55/Aksoy_EtAl_Logic_Synthesis_for_Switching_Lattices_under_Delay_Constraint.pdf]]</span>
 
<br>
 
<br>
−
[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Paper]]
+
[[Media:Aksoy_EtAl_Logic_Synthesis_for_Switching_Lattices_under_Delay_Constraint.pdf | Paper]]
 
|}
 
|}
  
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.pdf | A Novel Method for the Realization of Complex Logic Functions Using Switching Lattices]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Levent Aksoy and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| [http://iscas2020.org/ IEEE International Symposium on Circuits and Systems (ISCAS)], Seville, Spain, 2020.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/72/Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.pdf]]</span>
 +
<br>
 +
[[Media:Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
  
−
{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
+
[[File:MP4.jpg|60px|link=https://www.ecc.itu.edu.tr/images/7/7c/Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.mp4]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/7/7c/Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.mp4 Slides]
 +
|}
  
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 
|- valign=top
 
|- valign=top
−
| width="696" |'''Selected Publication'''
+
| width="100" |'''title''':
 +
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Levent Aksoy and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], Vol. 69, Issue 3, pp. 427&ndash;440, 2020.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]</span>
 +
<br>
 +
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
 
|}
 
|}
−
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 
  
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Levent Aksoy and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]</span>
 +
<br>
 +
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
|
 
|
 
{|  
 
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
−
| width="524"|[[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Synthesizing Logic with Percolation in Nanoscale Lattices]]
+
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
−
| [[Mustafa Altun]] and [http://cadbio.com/wiki/index.php/Marc_Riedel Marc Riedel]
+
| Ceylan Morgul and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
 
| '''appeared&nbsp;in''':
 
| '''appeared&nbsp;in''':
−
| [http://www.igi-global.com/Bookstore/TitleDetails.aspx?TitleId=1117&DetailsType=Description/ International Journal of Nanotechnology and Molecular Computation], <br>Vol. 3, Issue 2, pp. 12&ndash;30, 2011.
+
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal],  Vol. 64, pp. 60&ndash;70, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]</span>
 +
<br>
 +
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Logic Synthesis for Switching Lattices]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]] and Marc Riedel
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], Vol. 61, Issue 11, pp. 1588&ndash;1600, 2012.
 +
<!-- |- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="624"| [http://fias.uni-frankfurt.de International Conference on Computational Modelling of Nanostructured Materials (ICCMNM)-FIAS], Frankfurt, Germany, 2013. -->
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/ca/Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Paper]]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Synthesizing Logic with Percolation in Nanoscale Lattices]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]] and Marc Riedel
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://www.igi-global.com/Bookstore/TitleDetails.aspx?TitleId=1117&DetailsType=Description/ International Journal of Nanotechnology and Molecular Computation], Vol. 3, Issue 2, pp. 12&ndash;30, 2011.
 
|}
 
|}
  
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|}
 
|}
  
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf | Lattice Based Computation of Boolean Functions]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]] and Marc Riedel
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| [http://www.dac.com IEEE/ACM Design Automation Conference (DAC)], Anaheim, USA, 2010.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7b/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
  
−
{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
+
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt Slides]
 +
|}
  
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 
|- valign=top
 
|- valign=top
−
| width="696" |'''Selected Publication'''
+
| width="100" |'''title''':
 +
| width="550"|[[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Nanoscale Digital Computation Through Percolation]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]], Marc Riedel, and [http://www.cbs.umn.edu/eeb/contacts/claudia-neuhauser/ Claudia Neuhauser]
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| [http://www.dac.com IEEE/ACM Design Automation Conference (DAC)], San Francisco, USA, 2009.
 
|}
 
|}
−
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 
  
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0c/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt Slides]
 +
|}
 +
 +
== Energy Efficient ANN Hardware Implementation ==
 +
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
|
 
|
 
{|  
 
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
−
| width="450"|[[Media:Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf | Lattice Based Computation of Boolean Functions]]
+
| width="624"|[[Media:Nojehdeh_Altun_Approximate_ANN_2023.pdf | Energy Efficient Hardware Implementation of Fully-Connected Artificial Neural Networks Using Approximate Arithmetic Blocks]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
−
| [[Mustafa Altun]] and [http://cadbio.com/wiki/index.php/Marc_Riedel Marc Riedel]
+
| Mohammadreza Nojehdeh and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| width="624" | [https://www.springer.com/journal/34 Circuits, Systems, and Signal Processing], Vol. 42, Issue 9, pp. 5428&ndash;5452, 2023
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/1/16/Nojehdeh_Altun_Approximate_ANN_2023.pdf]]</span>
 +
<br>
 +
[[Media:Nojehdeh_Altun_Approximate_ANN_2023.pdf | Paper]]
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Karadeniz_Altun_TALIPOT.pdf | TALIPOT: Energy Efficient DNN Booster Employing Hybrid Bit Parallel-Serial Processing in MSB-First Fashion]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Burak Karadeniz and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 41, Issue 8, pp. 2714&ndash;2727, 2022
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/01/Karadeniz_Altun_TALIPOT.pdf]]</span>
 +
<br>
 +
[[Media:Karadeniz_Altun_TALIPOT.pdf | Paper]]
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Nojehdeh_Parvin_Altun_ANN_Implementation_with_MAC.pdf | Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Mohammadreza Nojehdeh, Sajjad Parvin, and [[Mustafa Altun]]
 +
|- valign=top
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
−
| [http://www.dac.com Design Automation Conference], Anaheim, CA, 2010.
+
| [http://www.eng.ucy.ac.cy/theocharides/isvlsi21/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Tampa, USA, 2021.
 
|}
 
|}
 +
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
−
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7b/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/4/41/Nojehdeh_Parvin_Altun_ANN_Implementation_with_MAC.pdf]]</span>
 
<br>
 
<br>
−
[[Media:Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf | Paper]]
+
[[Media:Nojehdeh_Parvin_Altun_ANN_Implementation_with_MAC.pdf | Paper]]
 
| align="center" width="70" |  
 
| align="center" width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
  
−
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt]]
+
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/b/bf/Nojehdeh_Parvin_Altun_ANN_Implementation_with_MAC.pptx]]
 
</span>
 
</span>
−
<br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt Slides]
+
<br> [https://www.ecc.itu.edu.tr/images/b/bf/Nojehdeh_Parvin_Altun_ANN_Implementation_with_MAC.pptx Slides]
 
|}
 
|}
  
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Parvin_Altun_Hardware_Aware_ANN_Training.pdf | A Study on Hardware-Aware Training Techniques for Feedforward Artificial Neural Networks]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Sajjad Parvin and [[Mustafa Altun]]
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| [http://www.eng.ucy.ac.cy/theocharides/isvlsi21/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Tampa, USA, 2021.
 +
|}
  
−
{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
+
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/9/95/Parvin_Altun_Hardware_Aware_ANN_Training.pdf]]</span>
 +
<br>
 +
[[Media:Parvin_Altun_Hardware_Aware_ANN_Training.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
  
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/c/cb/Parvin_Altun_Hardware_Aware_ANN_Training.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/c/cb/Parvin_Altun_Hardware_Aware_ANN_Training.pptx Slides]
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 
|- valign=top
 
|- valign=top
−
| width="696" |'''Selected Publication'''
+
| width="100" |'''title''':
 +
| width="550"|[[Media:Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pdf | Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Levent Aksoy, Sajjad Parvin, Mohammadreza Nojehdeh, and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| [http://iscas2020.org/ IEEE International Symposium on Circuits and Systems (ISCAS)], Seville, Spain, 2020.
 
|}
 
|}
−
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
+
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/eb/Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pdf]]</span>
 +
<br>
 +
[[Media:Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/3/3a/Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/3/3a/Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pptx Slides]
 +
|}
 +
 
 +
== Computing with Nano-Crossbar Arrays ==
 +
 
 +
=== Comprehensive Performance Optimization===
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
  
 
|
 
|
Line 100: Line 425:
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
−
| width="450"|[[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Nanoscale Digital Computation Through Percolation]]
+
| width="550"|[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
−
| [[Mustafa Altun]] and [http://cadbio.com/wiki/index.php/Marc_Riedel Marc Riedel]
+
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Lorena Anghel, Valentina Ciriani, Ioana Vatajelu, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and [[Mustafa Altun]]  
 
|- valign=top
 
|- valign=top
 +
| '''appeared&nbsp;in''':
 +
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=7729 IEEE Transactions on Nanotechnology], Vol. 20, pp. 39&ndash;53 2021.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf]]</span>
 +
<br>
 +
[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Paper]]
 +
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Nano-Crossbar based Computing: Lessons Learned and Future Directions]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]], Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz
 +
|- valign="top"
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
−
| [http://www.dac.com Design Automation Conference], San Francisco, CA, 2009.
+
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
 
|}
 
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/04/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf]]</span>
 +
<br>
 +
[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
  
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx Slides]
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
 +
|- valign="top"
 +
| '''authors''':
 +
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
 +
|}
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
−
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0c/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]</span>
 
<br>
 
<br>
−
[[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Paper]]
+
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
 
| align="center" width="70" |  
 
| align="center" width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
  
−
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt]]
+
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]
 
</span>
 
</span>
−
<br> [http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt Slides]
+
<br> [https://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
 
|}
 
|}
  
−
== Mathematics ==
+
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Onur Tunali and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]</span>
 +
<br>
 +
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
 +
|- valign="top"
 +
| '''authors''':
 +
| width="550"| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
 +
|- valign=top
 +
| '''appeared&nbsp;in''':
 +
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14&ndash;25, 2017.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]</span>
 +
<br>
 +
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]
 +
 
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]], Valentina Ciriani, and Mehdi Tahoori
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
 +
|- valign="top"
 +
| '''authors''':
 +
| width="550"| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]</span>
 +
<br>
 +
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PDF.png|65px|link=https://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]
 +
</span>
 +
<br> [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Ceylan Morgul, Furkan Peker, and [[Mustafa Altun]]
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| [http://www.eng.ucy.ac.cy/theocharides/isvlsi16/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]</span>
 +
<br>
 +
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
 +
|}
 +
 
 +
=== Logic Synthesis and Fault/Variation Tolerance ===
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Onur Tunali and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], Vol. 7, Issue 4, pp. 518&ndash;529, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]</span>
 +
<br>
 +
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Onur Tunali, Ceylan Morgul, and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22&ndash;31, 2018.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]</span>
 +
<br>
 +
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Furkan Peker and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522&ndash;532, 2018.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]</span>
 +
<br>
 +
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Onur Tunali and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]</span>
 +
<br>
 +
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Onur Tunali and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6,  Article 79, 2017.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]</span>
 +
<br>
 +
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Onur Tunali and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747&ndash;760, 2017.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]</span>
 +
<br>
 +
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf | Defect Tolerance in Diode FET and Four-Terminal Switch Based Nano-Crossbar Arrays]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Onur Tunali and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Boston, USA, 2015.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/ee/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf]]</span>
 +
<br>
 +
[[Media:Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/f/f9/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/f/f9/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pptx Slides]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Ceylan Morgul and [[Mustafa Altun]]
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]</span>
 +
<br>
 +
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
 +
|}
 +
 
 +
==== National Publications in Turkish ====
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf | Logic Circuit Design with Switching Nano Arrays and Area Optimization]]
 +
|- valign="top
 +
| width="100" |'''title (in Turkish)''':
 +
| width="550"|[[Media:Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf | Anahtarlamalı Nano Dizinler ile Lojik Devre Tasarımı ve Boyut Optimizasyonu]]
 +
|- valign="top
 +
| '''authors''':
 +
| Ceylan Morgul and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented at''':
 +
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2014.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/9/99/Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf]]</span>
 +
<br>
 +
[[Media:Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf  | Paper]]
 +
 
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/a/aa/Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/a/aa/Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pptx Slides]
 +
|}
 +
 
 +
== Stochastic and Bit Stream Computing ==
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Karadeniz_Cevik_Altun_STAMP_Stochastic_Number_Generator.pdf | STAMP: A Real-Time and Low-Power Sampling Error Based Stochastic Number Generator]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Burak Karadeniz, Ismail Cevik, and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared &nbsp;in''':
 +
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639 IEEE Access], Vol. 9, pp. 151363&ndash;151372, 2021.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/dd/Karadeniz_Cevik_Altun_STAMP_Stochastic_Number_Generator.pdf]]</span>
 +
<br>
 +
[[Media:Karadeniz_Cevik_Altun_STAMP_Stochastic_Number_Generator.pdf  | Paper]]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Vahapoglu_Altun_From_Stochastic_To_Bit_Stream_Computing.pdf | From Stochastic to Bit Stream Computing: Accurate Implementation of Arithmetic Circuits and Applications in Neural Networks]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Ensar Vahapoglu and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| width="624" | arXiv, 1805.06262, 2018.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/73/Vahapoglu_Altun_From_Stochastic_To_Bit_Stream_Computing.pdf]]</span>
 +
<br>
 +
[[Media:Vahapoglu_Altun_From_Stochastic_To_Bit_Stream_Computing.pdf | Paper]]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Karadeniz_Altun_Stochastic_Number_Generator.pdf| Sampling Based Random Number Generator for Stochastic Computing]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Burak Karadeniz and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/1/17/Karadeniz_Altun_Stochastic_Number_Generator.pdf]]</span>
 +
<br>
 +
[[Media:Karadeniz_Altun_Stochastic_Number_Generator.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/a/ab/Karadeniz_Altun_Stochastic_Number_Generator.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/a/ab/Karadeniz_Altun_Stochastic_Number_Generator.pptx Slides]
 +
 
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Vahapoglu_Altun_Accurate_Synthesis_of_Arithmetic_Operations_with_Stochastic_Logic.pdf | Accurate Synthesis of Arithmetic Operations with Stochastic Logic]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Ensar Vahapoglu and [[Mustafa Altun]]
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| [http://www.eng.ucy.ac.cy/theocharides/isvlsi16/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/d6/Vahapoglu_Altun_Accurate_Synthesis_of_Arithmetic_Operations_with_Stochastic_Logic.pdf]]</span>
 +
<br>
 +
[[Media:Vahapoglu_Altun_Accurate_Synthesis_of_Arithmetic_Operations_with_Stochastic_Logic.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/d/d6/Vahapoglu_Altun_Accurate_Synthesis_of_Arithmetic_Operations_with_Stochastic_Logic.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/d/d6/Vahapoglu_Altun_Accurate_Synthesis_of_Arithmetic_Operations_with_Stochastic_Logic.pptx Poster]
 +
|}
 +
 
 +
==== National Publications in Turkish ====
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Yavuz_Altun_Stokastik_Hesaplamada_Hata_Oranlarini_Azaltmak_icin_Rastgele_Bit_Karistirma_Yontemi.pdf | Random Bit Shuffling Method for Reducing Error Rates in Stochastic Computing]]
 +
|- valign="top"
 +
| width="100" |'''title (in Turkish)''':
 +
| width="550"|[[Media:Yavuz_Altun_Stokastik_Hesaplamada_Hata_Oranlarini_Azaltmak_icin_Rastgele_Bit_Karistirma_Yontemi.pdf | Stokastik Hesaplamada Hata Oranlarını Azaltmak için Rastgele Bit Karıştırma Yöntemi]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Serter Yavuz and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented at''':
 +
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyum (ELECO)], Bursa, Turkey, 2014.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e1/Yavuz_Altun_Stokastik_Hesaplamada_Hata_Oranlarini_Azaltmak_icin_Rastgele_Bit_Karistirma_Yontemi.pdf]]</span>
 +
<br>
 +
[[Media:Yavuz_Altun_Stokastik_Hesaplamada_Hata_Oranlarini_Azaltmak_icin_Rastgele_Bit_Karistirma_Yontemi.pdf  | Paper]]
 +
 
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/f/f0/Yavuz_Altun_Stokastik_Hesaplamada_Hata_Oranlarini_Azaltmak_icin_Rastgele_Bit_Karistirma_Yontemi.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/f/f0/Yavuz_Altun_Stokastik_Hesaplamada_Hata_Oranlarini_Azaltmak_icin_Rastgele_Bit_Karistirma_Yontemi.pptx Slides]
 +
|}
 +
 
 +
== Approximate Computing ==
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Nojehdeh_Aksoy_Altun_Approximate_ANN.pdf | Efficient Hardware Implementation of Artificial Neural Networks Using Approximate Multiply-Accumulate Blocks]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Mohammadreza Nojehdeh, Levent Aksoy, and [[Mustafa Altun]]
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| [http://www.eng.ucy.ac.cy/theocharides/isvlsi20/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Limassol, Cyprus, 2020.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bd/Nojehdeh_Aksoy_Altun_Approximate_ANN.pdf]]</span>
 +
<br>
 +
[[Media:Nojehdeh_Aksoy_Altun_Approximate_ANN.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/7/7f/Nojehdeh_Aksoy_Altun_Approximate_ANN.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/7/7f/Nojehdeh_Aksoy_Altun_Approximate_ANN.pptx Slides]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf | Systematic Synthesis of Approximate Adders and Multipliers with Accurate Error Calculations]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Mohammadreza Nojehdeh and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 70, pp. 99&ndash;107, 2020.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c8/Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf]]</span>
 +
<br>
 +
[[Media:Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf | Paper]]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf| Circuit Aware Approximate System Design with Case Studies in Image Processing and Neural Networks]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Tuba Ayhan and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639 IEEE Access], Vol. 7, pp. 4726&ndash;4734, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/9/90/Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf]]</span>
 +
<br>
 +
[[Media:Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf | Paper]]
 +
 
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Ayhan_Altun_Approximate_Neural_Network_Generation.pdf | Approximate Fully Connected Neural Network Generation ]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Tuba Ayhan and [[Mustafa Altun]]
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://smacd-conference.org/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Prague, Czech Republic, 2018.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ad/Ayhan_Altun_Approximate_Neural_Network_Generation.pdf]]</span>
 +
<br>
 +
[[Media:Ayhan_Altun_Approximate_Neural_Network_Generation.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/a/a4/Ayhan_Altun_Approximate_Neural_Network_Generation.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/a/a4/Ayhan_Altun_Approximate_Neural_Network_Generation.pptx Slides]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Ayhan_Kula_Altun_Approximate_System_Design_Methodology.pdf | A Power Efficient System Design Methodology Employing Approximate Arithmetic Units]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Tuba Ayhan, Firat Kula, and [[Mustafa Altun]]
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| [http://www.eng.ucy.ac.cy/theocharides/isvlsi17/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Bochum, Germany, 2017.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b4/Ayhan_Kula_Altun_Approximate_System_Design_Methodology.pdf]]</span>
 +
<br>
 +
[[Media:Ayhan_Kula_Altun_Approximate_System_Design_Methodology.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/8/86/Ayhan_Kula_Altun_Approximate_System_Design_Methodology.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/8/86/Ayhan_Kula_Altun_Approximate_System_Design_Methodology.pptx Slides]
 +
|}
 +
 
 +
==== National Publications in Turkish ====
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Kula_Ayhan_Altun_Approximate_FIR_Filter_Implementation.pdf | Approximate Implementation of FIR Filters on FPGA]]
 +
|- valign="top
 +
| width="100" |'''title (in Turkish)''':
 +
| width="550"|[[Media:Kula_Ayhan_Altun_Approximate_FIR_Filter_Implementation.pdf | FPGA Üzerinde Yaklaşık FIR Süzgeç Tasarımı]]
 +
|- valign="top
 +
| '''authors''':
 +
| Firat Kula, Tuba Ayhan, and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented at''':
 +
| width="550"| [http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1001786 Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU)], Izmir, Turkey, 2018.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e8/Kula_Ayhan_Altun_Approximate_FIR_Filter_Implementation.pdf]]</span>
 +
<br>
 +
[[Media:Kula_Ayhan_Altun_Approximate_FIR_Filter_Implementation.pdf  | Paper]]
 +
 
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/5/58/Kula_Ayhan_Altun_Approximate_FIR_Filter_Implementation.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/5/58/Kula_Ayhan_Altun_Approximate_FIR_Filter_Implementation.pptx Slides]
 +
|}
 +
 
 +
== Large-Area Electronics ==
 +
 
 +
=== Transistor Fabrication ===
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Yedikardes_Altun_Zayim_Investigation_of_P3HT.pdf| Investigation of P3HT:WO3 Hybrid Electrochromic Thin Films Prepared by Solution Blending Doping]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Beyza Yedikardes, [[Mustafa Altun]], and Esra Zayim
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [https://www.sciencedirect.com/journal/synthetic-metals Synthetic Metals], Vol. 297, Article 117407, 2023.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b2/Yedikardes_Altun_Zayim_Investigation_of_P3HT.pdf]]</span>
 +
<br>
 +
[[Media:Yedikardes_Altun_Zayim_Investigation_of_P3HT.pdf | Paper]]
 +
 
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Ordokhani_EtAl_SWCNT_Fabrication_with_Sonication.pdf| Improving Threshold Voltage and ON/OFF Current Ratio of Single-Walled Carbon Nanotube Field-Effect Transistor by Post-Sonication Treatments
 +
]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Fereshteh Ordokhani, Beyza Yedikardes, Ece Kurt, Nihat Akkan, Nilgün Yavuz, Esra Zayim, and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://www.journals.elsevier.com/thin-solid-films Thin Solid Films], Vol. 727, Article 138677, 2021.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/5e/Ordokhani_EtAl_SWCNT_Fabrication_with_Sonication.pdf]]</span>
 +
<br>
 +
[[Media:Ordokhani_EtAl_SWCNT_Fabrication_with_Sonication.pdf | Paper]]
 +
 
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pdf | Enhanced Electrical Properties of P3HT:WO3 Hybrid Thin Film Transistors]]
 +
|- valign="top"
 +
| '''authors''':
 +
| width="550"|Beyza Yedikardes, Fereshteh Ordokhani, Nihat Akkan, Ece Kurt, Esra Zayim, Nilgün Yavuz, and [[Mustafa Altun]]
 +
|- valign=top
 +
| '''appeared&nbsp;in''':
 +
| width="550"| [http://www.springer.com/journal/11664 Journal of Electronic Materials], Vol. 50, Issue 4, pp. 2466&ndash;2475, 2021.
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://www.advanced-nanomaterials-conference.com/ International Conference on Advanced Nanomaterials (ANM)], Aveiro, Portugal, 2019.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/d5/Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pdf]]</span>
 +
<br>
 +
[[Media:Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/2/25/Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/2/25/Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pptx Slides]
 +
|}
 +
 
 +
=== Organic Transistor Modeling ===
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Akkan_Altun_Sedef_Behavioral_OTFT_Modeling.pdf| Behavioral Modeling for Low-Voltage Pentacene-Based OTFTs and Their Implementations for Organic Logic Circuits
 +
]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Nihat Akkan, [[Mustafa Altun]], and Herman Sedef
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [https://www.sciencedirect.com/journal/engineering-science-and-technology-an-international-journal Engineering Science and Technology, an International Journal], Vol. 37, Article 101317, 2023.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/35/Akkan_Altun_Sedef_Behavioral_OTFT_Modeling.pdf]]</span>
 +
<br>
 +
[[Media:Akkan_Altun_Sedef_Behavioral_OTFT_Modeling.pdf | Paper]]
 +
 
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Akkan_Sedef_Altun_TFT_Level_3_Spice_Model.pdf | The Level 3 Based SPICE Model for Low-Voltage Pentacene Thin Film Transistors]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Nihat Akkan, [[Mustafa Altun]], and Herman Sedef
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://smacd-conference.org/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Sardinia, Italy, 2022.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c1/Akkan_Sedef_Altun_TFT_Level_3_Spice_Model.pdf]]</span>
 +
<br>
 +
[[Media:Akkan_Sedef_Altun_TFT_Level_3_Spice_Model.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/6/6e/Akkan_Sedef_Altun_TFT_Level_3_Spice_Model.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/6/6e/Akkan_Sedef_Altun_TFT_Level_3_Spice_Model.pptx Slides]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Akkan_Altun_Sedef_OFET_Modelling_IEEE_Access.pdf| Modeling and Parameter Extraction of OFET Compact Models Using Metaheuristics-Based Approach
 +
]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Nihat Akkan, [[Mustafa Altun]], and Herman Sedef
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639 IEEE Access], Vol. 7, pp. 180438&ndash;180450, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/5c/Akkan_Altun_Sedef_OFET_Modelling_IEEE_Access.pdf]]</span>
 +
<br>
 +
[[Media:Akkan_Altun_Sedef_OFET_Modelling_IEEE_Access.pdf | Paper]]
 +
 
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Akkan_Altun_Sedef_OFET_Parameter_Extraction_with_ABC.pdf | Parameter Extraction Method Using Hybrid Artificial Bee Colony Algorithm for an OFET Compact Model ]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Nihat Akkan, [[Mustafa Altun]], and Herman Sedef
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://smacd-conference.org/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Prague, Czech Republic, 2018.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/1/15/Akkan_Altun_Sedef_OFET_Parameter_Extraction_with_ABC.pdf]]</span>
 +
<br>
 +
[[Media:Akkan_Altun_Sedef_OFET_Parameter_Extraction_with_ABC.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/b/b9/Akkan_Altun_Sedef_OFET_Parameter_Extraction_with_ABC.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/b/b9/Akkan_Altun_Sedef_OFET_Parameter_Extraction_with_ABC.pptx Slides]
 +
|}
 +
 
 +
== Reversible Computing ==
 +
 
 +
=== CMOS Fault Tolerance ===
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Parvin_Altun_Perfect_Concurrent_Fault_Detection.pdf| Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates
 +
]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Sajjad Parvin and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639 IEEE Access], Vol. 7, pp. 163939&ndash;163947, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/3c/Parvin_Altun_Perfect_Concurrent_Fault_Detection.pdf]]</span>
 +
<br>
 +
[[Media:Parvin_Altun_Perfect_Concurrent_Fault_Detection.pdf | Paper]]
 +
 
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf | Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Sajjad Parvin and [[Mustafa Altun]]
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://tima.univ-grenoble-alpes.fr/conferences/iolts/iolts19/ IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)], Rhodes Island, Greece, 2019.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/ee/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf]]</span>
 +
<br>
 +
[[Media:Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/f/f4/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/f/f4/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pptx Poster]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf| Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits
 +
]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]], Sajjad Parvin, and Husrev Cilasun
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639 IEEE Access], Vol. 6, pp. 74475&ndash;74484, 2018.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7d/Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf | Paper]]
 +
 
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Cilasun_Altun_A_Novel_Reversible_Fault_Tolerant_Microprocessor.pdf| A Novel Reversible Fault Tolerant Microprocessor Design in AMS 0.35um Process
 +
]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Husrev Cilasun and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://www.journals.istanbul.edu.tr/iujeee/index Istanbul University - Journal of Electrical & Electronics Engineering], Vol. 17, No. 1, pp. 3147&ndash;3154,  2017.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/30/Cilasun_Altun_A_Novel_Reversible_Fault_Tolerant_Microprocessor.pdf]]</span>
 +
<br>
 +
[[Media:Cilasun_Altun_A_Novel_Reversible_Fault_Tolerant_Microprocessor.pdf | Paper]]
 +
 
 +
|}
 +
 
 +
=== Logic Synthesis ===
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf| Fast Synthesis of Reversible Circuits using a Sorting Algorithm and Optimization]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Omercan Susam and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://www.oldcitypublishing.com/journals/mvlsc-home/ Journal of Multiple-Valued Logic and Soft Computing], Vol. 29, Issue 1-2, pp. 1&ndash;23, 2017.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cd/Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf]]</span>
 +
<br>
 +
[[Media:Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf | Paper]]
 +
 
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pdf| An Efficient Algorithm to Synthesize Quantum Circuits and Optimization]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Omercan Susam and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://www.ieee-icecs2014.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Marseille, France, 2014.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pdf]]</span>
 +
<br>
 +
[[Media:Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/d/d0/Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/d/d0/Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pptx Slides]
 +
|}
 +
 
 +
==== National Publications in Turkish ====
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pdf | Kuantum Devre Sentezi ve Optimizasyonu için Verimli bir Algoritma]]
 +
|- valign="top
 +
| '''authors''':
 +
| Omercan Susam and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented at''':
 +
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2014.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pdf]]</span>
 +
<br>
 +
[[Media:Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pdf  | Paper]]
 +
 
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/3/38/Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/3/38/Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pptx Slides]
 +
|}
 +
 
 +
== Reliability of Electronic Products ==
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media: Yadavari_Altun_Distinct_Degradation_Processes_in_ZnO_varistors.pdf| Distinct Degradation Processes in ZnO Varistors: Reliability Analysis and Modeling with Accelerated AC Tests]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Hadi Yadavari and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://journals.tubitak.gov.tr/elektrik/index.htm;jsessionid=848207EBE52EFE10C78B78C76A0FEAD9 Turkish Journal of Electrical Engineering and Computer Sciences], Vol. 25, No. 4, pp. 3240&ndash;3252, 2017.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/dd/Yadavari_Altun_Distinct_Degradation_Processes_in_ZnO_varistors.pdf]]</span>
 +
<br>
 +
[[Media:Yadavari_Altun_Distinct_Degradation_Processes_in_ZnO_varistors.pdf | Paper]]
 +
 
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Altun_Comert_A_Change-Point_based_Reliability_Prediction_Model_using_Field_Return_Data.pdf| A Change-Point based Reliability Prediction Model using Field Return Data]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]] and Vehbi Comert
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://www.journals.elsevier.com/reliability-engineering-and-system-safety Reliability Engineering and System Safety], Vol. 156, pp. 175&ndash;184, 2016.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/1/16/Altun_Comert_A_Change-Point_based_Reliability_Prediction_Model_using_Field_Return_Data.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Comert_A_Change-Point_based_Reliability_Prediction_Model_using_Field_Return_Data.pdf | Paper]]
 +
 
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Yadavari_EtAl_Effects_of_ZnO_Varistor_Degradation_on_the_Overvoltage_Protection_Mechanism_of_Electronic_Boards.pdf | Effects of ZnO Varistor Degradation on the Overvoltage Protection Mechanism of Electronic Boards]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Hadi Yadavari, Burak Sal, [[Mustafa Altun]], Ertunc Erturk, and Baris Ocak
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| [http://esrel2015.ethz.ch/ European Safety and Reliability Conference (ESREL)], Zurich, Switzerland, 2015.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/d7/Yadavari_EtAl_Effects_of_ZnO_Varistor_Degradation_on_the_Overvoltage_Protection_Mechanism_of_Electronic_Boards.pdf]]</span>
 +
<br>
 +
[[Media:Yadavari_EtAl_Effects_of_ZnO_Varistor_Degradation_on_the_Overvoltage_Protection_Mechanism_of_Electronic_Boards.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/d/de/Yadavari_EtAl_Effects_of_ZnO_Varistor_Degradation_on_the_Overvoltage_Protection_Mechanism_of_Electronic_Boards.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/d/de/Yadavari_EtAl_Effects_of_ZnO_Varistor_Degradation_on_the_Overvoltage_Protection_Mechanism_of_Electronic_Boards.pptx Slides]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Sal_Altun_Extensive_Investigation_of_CALT_in_Comparison_with_ALT.pdf | Extensive Investigation of Calibrated Accelerated Life Testing (CALT) in Comparison with Classical Accelerated Life Testing (ALT)]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Burak Sal and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| [http://esrel2015.ethz.ch/ European Safety and Reliability Conference (ESREL)], Zurich, Switzerland, 2015.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/07/Sal_Altun_Extensive_Investigation_of_CALT_in_Comparison_with_ALT.pdf]]</span>
 +
<br>
 +
[[Media:Sal_Altun_Extensive_Investigation_of_CALT_in_Comparison_with_ALT.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/a/a8/Sal_Altun_Extensive_Investigation_of_CALT_in_Comparison_with_ALT.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/a/a8/Sal_Altun_Extensive_Investigation_of_CALT_in_Comparison_with_ALT.pptx Slides]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Comert_Altun_Nadar_Erturk_Warranty_Forecasting_of_Electronic_Boards_using_Short-term_Field_Data.pdf | Warranty Forecasting of Electronic Boards using Short-term Field Data]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Vehbi Comert, [[Mustafa Altun]], Mustafa Nadar, and Ertunc Erturk
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| [http://rams.org/ Reliability and Maintainability Symposium (RAMS)], Palm Harbor, USA, 2015.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fd/Comert_Altun_Nadar_Erturk_Warranty_Forecasting_of_Electronic_Boards_using_Short-term_Field_Data.pdf]]</span>
 +
<br>
 +
[[Media:Comert_Altun_Nadar_Erturk_Warranty_Forecasting_of_Electronic_Boards_using_Short-term_Field_Data.pdf| Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/a/a7/Comert_Altun_Nadar_Erturk_Warranty_Forecasting_of_Electronic_Boards_using_Short-term_Field_Data.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/a/a7/Comert_Altun_Nadar_Erturk_Warranty_Forecasting_of_Electronic_Boards_using_Short-term_Field_Data.pptx Slides]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Comert_Yadavari_Altun_Erturk_Reliability_Prediction_of_Electronic_Boards_by_Analyzing_Field_Return_Data.pdf | Reliability Prediction of Electronic Boards by Analyzing Field Return Data]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Vehbi Comert, Hadi Yadavari, [[Mustafa Altun]], and Ertunc Erturk
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| [http://www.esrel2014.org/ European Safety and Reliability Conference (ESREL)], Wroclaw, Poland, 2014.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/d4/Comert_Yadavari_Altun_Erturk_Reliability_Prediction_of_Electronic_Boards_by_Analyzing_Field_Return_Data.pdf]]</span>
 +
<br>
 +
[[Media:Comert_Yadavari_Altun_Erturk_Reliability_Prediction_of_Electronic_Boards_by_Analyzing_Field_Return_Data.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/e/eb/Comert_Yadavari_Altun_Erturk_Reliability_Prediction_of_Electronic_Boards_by_Analyzing_Field_Return_Data.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/e/eb/Comert_Yadavari_Altun_Erturk_Reliability_Prediction_of_Electronic_Boards_by_Analyzing_Field_Return_Data.pptx Slides]
 +
|}
 +
 
 +
==== National Publications in Turkish ====
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Avci_Altun_Reliability Model_for_MOSFET_GOB.pdf | A New Reliability Model for MOSFET Gate Oxide Breakdown]]
 +
|- valign="top
 +
| width="100" |'''title (in Turkish)''':
 +
| width="550"|[[Media:Avci_Altun_Reliability_Model_for_MOSFET_GOB.pdf | MOSFET Geçit Oksidi Kırılması için Yeni Bir Güvenilirlik Modeli]]
 +
|- valign="top
 +
| '''authors''':
 +
| Hasan Avci and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented at''':
 +
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2018.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6f/Avci_Altun_Reliability_Model_for_MOSFET_GOB.pdf]]</span>
 +
<br>
 +
[[Media:Avci_Altun_Reliability_Model_for_MOSFET_GOB.pdf  | Paper]]
 +
 
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/f/f9/Avci_Altun_Reliability_Model_for_MOSFET_GOB.pptx]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/f/f9/Avci_Altun_Reliability_Model_for_MOSFET_GOB.pptx Slides]
 +
|}
  
 
== Analog Circuit Design ==
 
== Analog Circuit Design ==
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Gungordu_Altun_Cevik_Positive_Feedback_Current_Buffer.pdf | Low Input Resistance Current Buffer Stage Using a Controllable Positive Feedback Loop, and Applications of Current Conveyor Based Filters]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Dogus Gungordu, [[Mustafa Altun]], and Ismail Cevik
 +
|- valign="top"
 +
| '''appeared &nbsp;in''':
 +
| [http://www.journals.elsevier.com/aeu-international-journal-of-electronics-and-communications/ AEU International Journal of Electronics and Communications], Vol. 82, pp. 58&ndash;65, 2017.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/05/Gungordu_Altun_Cevik_Positive_Feedback_Current_Buffer.pdf]]</span>
 +
<br>
 +
[[Media:Gungordu_Altun_Cevik_Positive_Feedback_Current_Buffer.pdf  | Paper]]
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Alaybeyoglu_Guney_Altun_Kuntman_Design_of_Positive_Feedback_Driven_Current-Mode_Amplifiers_Z-Copy_CDBA_and_CDTA_and_Filter_Applications.pdf | Design of Positive Feedback Driven Current-Mode Amplifiers Z-Copy CDBA and CDTA and Filter Applications]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Ersin Alaybeyoglu, Arda Guney, [[Mustafa Altun]], and Hakan Kuntman
 +
|- valign="top"
 +
| '''appeared &nbsp;in''':
 +
| [http://www.springer.com/engineering/circuits+%26+systems/journal/10470 Analog Integrated Circuits and Signal Processing], Vol. 81, Issue 1, pp. 109&ndash;120, 2014.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2f/Alaybeyoglu_Guney_Altun_Kuntman_Design_of_Positive_Feedback_Driven_Current-Mode_Amplifiers_Z-Copy_CDBA_and_CDTA_and_Filter_Applications.pdf]]</span>
 +
<br>
 +
[[Media:Alaybeyoglu_Guney_Altun_Kuntman_Design_of_Positive_Feedback_Driven_Current-Mode_Amplifiers_Z-Copy_CDBA_and_CDTA_and_Filter_Applications.pdf  | Paper]]
 +
|}
 +
<!--
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Alaybeyoglu_Guney_Altun_Kuntman_Low_Input_Impedance_Current_Differencing_Unit_for_Current_Mode_Active_Devices_Improved_by_Positive_Feedback_and_ZC-CDBA_Filter_Application.pdf | Low Input Impedance Current Differencing Unit for Current Mode Active Devices Improved by Positive Feedback and ZC-CDBA Filter Application]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Ersin Alaybeyoglu, Arda Guney, [[Mustafa Altun]], and Hakan Kuntman
 +
|- valign="top"
 +
| '''presented &nbsp;at''':
 +
| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2013.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/1/18/Alaybeyoglu_Guney_Altun_Kuntman_Low_Input_Impedance_Current_Differencing_Unit_for_Current_Mode_Active_Devices_Improved_by_Positive_Feedback_and_ZC-CDBA_Filter_Application.pdf]]</span>
 +
<br>
 +
[[Media:Alaybeyoglu_Guney_Altun_Kuntman_Low_Input_Impedance_Current_Differencing_Unit_for_Current_Mode_Active_Devices_Improved_by_Positive_Feedback_and_ZC-CDBA_Filter_Application.pdf  | Paper]]
 +
|}
 +
-->
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Altun_Kuntman_Minaei_Sayin_Realisation_of_nth_Order_Current_Transfer_Function_Employing_ECCIIs_and_Application_Examples.pdf | Realisation of nth Order Current Transfer Function Employing ECCIIs and Application Examples]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]], Hakan Kuntman, Shahram Minaei, and Onur Sayin
 +
|- valign="top"
 +
| '''appeared &nbsp;in''':
 +
| [http://www.tandfonline.com/toc/tetn20/current/ International Journal of Electronics], Vol. 96, Issue 11, pp. 1115&ndash;1126, 2009.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/9/99/Altun_Kuntman_Minaei_Sayin_Realisation_of_nth_Order_Current_Transfer_Function_Employing_ECCIIs_and_Application_Examples.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Kuntman_Minaei_Sayin_Realisation_of_nth_Order_Current_Transfer_Function_Employing_ECCIIs_and_Application_Examples.pdf  | Paper]]
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Altun_Kuntman_Design_of_a_Fully_Differential_Current_Mode_Operational_Amplifier_with_its_Filter_Applications.pdf | Design of a Fully Differential Current Mode Operational Amplifier with Improved Input-Output Impedances and its Filter Applications]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]] and Hakan Kuntman
 +
|- valign="top"
 +
| '''appeared &nbsp;in''':
 +
| [http://www.journals.elsevier.com/aeu-international-journal-of-electronics-and-communications/ AEU International Journal of Electronics and Communications], Vol. 62, Issue 3, pp. 39&ndash;44, 2008.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e5/Altun_Kuntman_Design_of_a_Fully_Differential_Current_Mode_Operational_Amplifier_with_its_Filter_Applications.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Kuntman_Design_of_a_Fully_Differential_Current_Mode_Operational_Amplifier_with_its_Filter_Applications.pdf  | Paper]]
 +
|}
 +
<!--
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Sayginer_Altun_Kuntman_A_CMOS_FTFN_Realization_with_Constant_gm_Rail_to_Rail_Input_Stage.pdf | A CMOS FTFN Realization with Constant-gm Rail-to-Rail Input Stage]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [http://web.itu.edu.tr/~sayginer/ Mustafa Sayginer], [[Mustafa Altun]], and Hakan Kuntman
 +
|- valign="top"
 +
| '''presented &nbsp;at''':
 +
| [http://www.melecon2012.org/ IEEE Mediterranean Electrotechnical Conference (MELECON)], Ajaccio, France, 2008.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/1/14/Sayginer_Altun_Kuntman_A_CMOS_FTFN_Realization_with_Constant_gm_Rail_to_Rail_Input_Stage.pdf]]</span>
 +
<br>
 +
[[Media:Sayginer_Altun_Kuntman_A_CMOS_FTFN_Realization_with_Constant_gm_Rail_to_Rail_Input_Stage.pdf  | Paper]]
 +
|}
 +
-->
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Altun_Kuntman_A_High_Drive_Fully_Differential_Current_Mode_Operational_Amplifier_Providing_High_Output_Impedance_and_Filter_Application.pdf | A High Drive Fully Differential Current Mode Operational Amplifier Providing High Output Impedance and Filter Application]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]] and Hakan Kuntman
 +
|- valign="top"
 +
| '''presented &nbsp;at''':
 +
| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2007.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/f1/Altun_Kuntman_A_High_Drive_Fully_Differential_Current_Mode_Operational_Amplifier_Providing_High_Output_Impedance_and_Filter_Application.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Kuntman_A_High_Drive_Fully_Differential_Current_Mode_Operational_Amplifier_Providing_High_Output_Impedance_and_Filter_Application.pdf  | Paper]]
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Altun_Kuntman_High_CMRR_Current_Mode_Operational_Amplifier_with_a_Novel_Class_AB_Input_Stage.pdf | High CMRR Current Mode Operational Amplifier with a Novel Class AB Input Stage]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]] and Hakan Kuntman
 +
|- valign="top"
 +
| '''presented &nbsp;at''':
 +
| [http://www.glsvlsi.org/ ACM Great Lakes Symposium on VLSI (GLSVLSI)], Stresa, Italy, 2007.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Altun_Kuntman_High_CMRR_Current_Mode_Operational_Amplifier_with_a_Novel_Class_AB_Input_Stage.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Kuntman_High_CMRR_Current_Mode_Operational_Amplifier_with_a_Novel_Class_AB_Input_Stage.pdf  | Paper]]
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Altun_Kuntman_A_Wideband_CMOS_Current_Mode_Operational_Amplifier_and_its_Use_for_Band_Pass_Filter_Realization.pdf | A Wideband CMOS Current Mode Operational Amplifier and its Use for Band Pass Filter Realization]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]] and Hakan Kuntman
 +
|- valign="top"
 +
| '''presented &nbsp;at''':
 +
| [http://www.appel.zcu.cz/ Applied Electronics (AE)], Pilsen, Czech Republic, 2006.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cd/Altun_Kuntman_A_Wideband_CMOS_Current_Mode_Operational_Amplifier_and_its_Use_for_Band_Pass_Filter_Realization.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Kuntman_A_Wideband_CMOS_Current_Mode_Operational_Amplifier_and_its_Use_for_Band_Pass_Filter_Realization.pdf  | Paper]]
 +
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/7/77/Altun_Kuntman_A_Wideband_CMOS_Current-Mode_Operational_Amplifier_and_Its_Use_for_Band-Pass_Filter_Realization.ppt]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/7/77/Altun_Kuntman_A_Wideband_CMOS_Current-Mode_Operational_Amplifier_and_Its_Use_for_Band-Pass_Filter_Realization.ppt Slides]
 +
|}
 +
 +
==== National Publications in Turkish ====
 +
 +
<!--
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Sayginer_Altun_Kuntman_Beslemeden_Beslemeye_Giris_Katli_Bir_CMOS_FTFN_Tasarimi_ve_Topraklanmis_Enduktans_Uygulamasi.pdf | Beslemeden Beslemeye Giriş Katlı bir CMOS FTFN Tasarımı ve Topraklanmış Endüktans Uygulaması]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [http://web.itu.edu.tr/~sayginer/ Mustafa Sayginer], [[Mustafa Altun]], and Hakan Kuntman
 +
|- valign="top"
 +
| '''presented at''':
 +
| [http://www.emo.org.tr/etkinlikler/ulusal/index.php?etkinlikkod=27 Biyomedikal Müh. 12. Ulusal Kongresi], Eskisehir, Turkey, 2007.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Sayginer_Altun_Kuntman_Beslemeden_Beslemeye_Giris_Katli_Bir_CMOS_FTFN_Tasarimi_ve_Topraklanmis_Enduktans_Uygulamasi.pdf]]</span>
 +
<br>
 +
[[Media:Sayginer_Altun_Kuntman_Beslemeden_Beslemeye_Giris_Katli_Bir_CMOS_FTFN_Tasarimi_ve_Topraklanmis_Enduktans_Uygulamasi.pdf  | Paper]]
 +
|}
 +
-->
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Altun_Kuntman_Yuksek_Basarimli_Tumuyle_Farksal_Akim_Modlu_Islemsel_Kuvvetlendirici_COA_Tasarimi_ve_Tum_Geciren_Suzgec_Yapisinda_Kullanimi.pdf | Yüksek Başarımlı Tümüyle Farksal Akım Modlu İşlemsel Kuvvetlendirici (COA) Tasarımı ve Tüm Geçiren Süzgeç Yapısında Kullanımı]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]] and Hakan Kuntman
 +
|- valign="top"
 +
| '''presented at''':
 +
| width="624"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2006.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/a5/Altun_Kuntman_Yuksek_Basarimli_Tumuyle_Farksal_Akim_Modlu_Islemsel_Kuvvetlendirici_COA_Tasarimi_ve_Tum_Geciren_Suzgec_Yapisinda_Kullanimi.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Kuntman_Yuksek_Basarimli_Tumuyle_Farksal_Akim_Modlu_Islemsel_Kuvvetlendirici_COA_Tasarimi_ve_Tum_Geciren_Suzgec_Yapisinda_Kullanimi.pdf  | Paper]]
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Altun_MSc_Thesis_Akim_Modlu_Islemsel_Kuvvetlendirici_Tasarimi_ve_Uygulamalari.pdf | Akım Modlu İşlemsel Kuvvetlendirici Tasarımı ve Uygulamaları]]
 +
|- valign="top"
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Altun_MSc_Thesis_Akim_Modlu_Islemsel_Kuvvetlendirici_Tasarimi_ve_Uygulamalari.pdf | Design of a Current Mode Operational Amplifier and Its Applications]]
 +
|- valign="top"
 +
| '''author''':
 +
| [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''thesis''':
 +
| MSc, [http://www.ehb.itu.edu.tr/index.php?lang=en Electronics Engineering], [http://www.itu.edu.tr/en/ Istanbul Technical University], 2007.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/3a/Altun_MSc_Thesis_Akim_Modlu_Islemsel_Kuvvetlendirici_Tasarimi_ve_Uygulamalari.pdf]]</span>
 +
<br>
 +
[[Media:Altun_MSc_Thesis_Akim_Modlu_Islemsel_Kuvvetlendirici_Tasarimi_ve_Uygulamalari.pdf  | Thesis]]
 +
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=https://www.ecc.itu.edu.tr/images/8/8d/Altun_MSc_Thesis_Akim_Modlu_Islemsel_Kuvvetlendirici_Tasarimi_ve_Uygulamalari.ppt]]
 +
</span>
 +
<br> [https://www.ecc.itu.edu.tr/images/8/8d/Altun_MSc_Thesis_Akim_Modlu_Islemsel_Kuvvetlendirici_Tasarimi_ve_Uygulamalari.ppt Slides]
 +
|}
 +
 +
== Discrete Mathematics ==
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Altun_Riedel_A_Study_on_Monotone_Self_Dual_Boolean_Functions.pdf | A Study on Monotone Self-dual Boolean Functions]]
 +
|- valign=top
 +
| '''authors''':
 +
| [[Mustafa Altun]] and Marc Riedel
 +
|- valign="top"
 +
| '''appeared &nbsp;in''':
 +
| [http://www.springer.com/mathematics/applications/journal/10255 Acta Mathematicae Applicatae Sinica - English Series], Vol. 33, Issue 1, pp. 43&ndash;52, 2017.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/53/Altun_Riedel_A_Study_on_Monotone_Self_Dual_Boolean_Functions.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Riedel_A_Study_on_Monotone_Self_Dual_Boolean_Functions.pdf  | Paper]]
 +
|}

Latest revision as of 15:25, 30 August 2023

Listed below are the papers, first authored by our group members as an indication that the related research is mainly conducted in our group, and the presentations. Research topics are ordered from newest to oldest as well as by considering their importance. Under each topic, papers are ordered from newest to oldest. All materials are subject to copyrights.

Contents

[edit] Computing with Switching Lattices

[edit] Technology Development

title: Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches
authors: Nihat Akkan, Serzat Safaltin, Levent Aksoy, Ismail Cevik, Herman Sedef, Csaba Andras Moritz, and Mustafa Altun
appeared in: IEEE Transactions on Emerging Topics in Computing, Vol. 10, Issue 1, pp. 351–360, 2022.

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Paper

title: CMOS Implementation of Switching Lattices
authors: Ismail Cevik, Levent Aksoy, and Mustafa Altun
presented at: Design, Automation, and Test in Europe (DATE), Grenoble, France, 2020.

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Paper

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Slides

title: Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling
authors: Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
presented at: Design, Automation and Test in Europe (DATE), Florence, Italy, 2019.

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Paper

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Slides

[edit] Logic Synthesis and Fault/Variation Tolerance

title: Realization of Logic Functions Using Switching Lattices Under a Delay Constraint
authors: Levent Aksoy, Nihat Akkan, Herman Sedef, and Mustafa Altun
appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 40, Issue 10, pp. 2036–2048, 2021.

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Paper

title: A Novel Method for the Realization of Complex Logic Functions Using Switching Lattices
authors: Levent Aksoy and Mustafa Altun
presented at: IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020.

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Paper

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Slides

title: Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices
authors: Levent Aksoy and Mustafa Altun
appeared in: IEEE Transactions on Computers, Vol. 69, Issue 3, pp. 427–440, 2020.

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Paper

title: A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices
authors: Levent Aksoy and Mustafa Altun
presented at: Design, Automation and Test in Europe (DATE), Florence, Italy, 2019.

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Paper

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Slides

title: Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches
authors: Ceylan Morgul and Mustafa Altun
appeared in: Integration, the VLSI Journal, Vol. 64, pp. 60–70, 2019.

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Paper

title: Logic Synthesis for Switching Lattices
authors: Mustafa Altun and Marc Riedel
appeared in: IEEE Transactions on Computers, Vol. 61, Issue 11, pp. 1588–1600, 2012.

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Paper

title: Synthesizing Logic with Percolation in Nanoscale Lattices
authors: Mustafa Altun and Marc Riedel
appeared in: International Journal of Nanotechnology and Molecular Computation, Vol. 3, Issue 2, pp. 12–30, 2011.

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Paper

title: Lattice Based Computation of Boolean Functions
authors: Mustafa Altun and Marc Riedel
presented at: IEEE/ACM Design Automation Conference (DAC), Anaheim, USA, 2010.

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Paper

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Slides

title: Nanoscale Digital Computation Through Percolation
authors: Mustafa Altun, Marc Riedel, and Claudia Neuhauser
presented at: IEEE/ACM Design Automation Conference (DAC), San Francisco, USA, 2009.

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Paper

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Slides

[edit] Energy Efficient ANN Hardware Implementation

title: Energy Efficient Hardware Implementation of Fully-Connected Artificial Neural Networks Using Approximate Arithmetic Blocks
authors: Mohammadreza Nojehdeh and Mustafa Altun
appeared in: Circuits, Systems, and Signal Processing, Vol. 42, Issue 9, pp. 5428–5452, 2023

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Paper

title: TALIPOT: Energy Efficient DNN Booster Employing Hybrid Bit Parallel-Serial Processing in MSB-First Fashion
authors: Burak Karadeniz and Mustafa Altun
appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 41, Issue 8, pp. 2714–2727, 2022

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Paper

title: Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks
authors: Mohammadreza Nojehdeh, Sajjad Parvin, and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, USA, 2021.

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Paper

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Slides

title: A Study on Hardware-Aware Training Techniques for Feedforward Artificial Neural Networks
authors: Sajjad Parvin and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, USA, 2021.

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Paper

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Slides

title: Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks
authors: Levent Aksoy, Sajjad Parvin, Mohammadreza Nojehdeh, and Mustafa Altun
presented at: IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020.

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Paper

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Slides

[edit] Computing with Nano-Crossbar Arrays

[edit] Comprehensive Performance Optimization

title: Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance
authors: Ceylan Morgul, Luca Frontini, Onur Tunali, Lorena Anghel, Valentina Ciriani, Ioana Vatajelu, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
appeared in: IEEE Transactions on Nanotechnology, Vol. 20, pp. 39–53 2021.

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Paper

title: Nano-Crossbar based Computing: Lessons Learned and Future Directions
authors: Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz
presented at: Design, Automation, and Test in Europe (DATE), Grenoble, France, 2020.

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Paper

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Slides

title: Integrated Synthesis Methodology for Crossbar Arrays
authors: Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
presented at: IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Athens, Greece, 2018.

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Paper

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Slides

title: Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
presented at: Design, Automation and Test in Europe (DATE), Dresden, Germany, 2018.

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Paper

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Slides

title: Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays
authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
appeared in: Microprocessors and Microsystems, Vol. 54, pp. 14–25, 2017.

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Paper

title: Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance
authors: Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
presented at: Design, Automation and Test in Europe (DATE), Lausanne, Switzerland, 2017.

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Paper

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Slides

title: Synthesis and Performance Optimization of a Switching Nano-crossbar Computer
authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016.

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Paper

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Slides

title: Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays
authors: Ceylan Morgul, Furkan Peker, and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016.

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Paper

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Poster

[edit] Logic Synthesis and Fault/Variation Tolerance

title: A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
appeared in: IEEE Transactions on Emerging Topics in Computing, Vol. 7, Issue 4, pp. 518–529, 2019.

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Paper

title: Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation
authors: Onur Tunali, Ceylan Morgul, and Mustafa Altun
appeared in: IEEE Micro, Vol. 38, Issue 5, pp. 22–31, 2018.

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Paper

title: A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays
authors: Furkan Peker and Mustafa Altun
appeared in: IEEE Transactions on Multi-Scale Computing Systems, Vol. 4, No. 4, pp. 522–532, 2018.

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Paper

title: Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions
authors: Onur Tunali and Mustafa Altun
presented at: IEEE International Conference on Electronics Circuits and Systems (ICECS), Batumi, Georgia, 2017.

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Paper

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Slides

title: A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
appeared in: ACM Computing Surveys, Vol. 50, No. 6, Article 79, 2017.

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Paper

title: Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, Issue 5, pp. 747–760, 2017.

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Paper

title: Defect Tolerance in Diode FET and Four-Terminal Switch Based Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
presented at: IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Boston, USA, 2015.

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Paper

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Slides

title: Synthesis and Optimization of Switching Nanoarrays
authors: Ceylan Morgul and Mustafa Altun
presented at: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Belgrade, Serbia, 2015.

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Paper

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Slides

[edit] National Publications in Turkish

title: Logic Circuit Design with Switching Nano Arrays and Area Optimization
title (in Turkish): Anahtarlamalı Nano Dizinler ile Lojik Devre Tasarımı ve Boyut Optimizasyonu
authors: Ceylan Morgul and Mustafa Altun
presented at: Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO), Bursa, Turkey, 2014.

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Paper

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Slides

[edit] Stochastic and Bit Stream Computing

title: STAMP: A Real-Time and Low-Power Sampling Error Based Stochastic Number Generator
authors: Burak Karadeniz, Ismail Cevik, and Mustafa Altun
appeared  in: IEEE Access, Vol. 9, pp. 151363–151372, 2021.

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Paper

title: From Stochastic to Bit Stream Computing: Accurate Implementation of Arithmetic Circuits and Applications in Neural Networks
authors: Ensar Vahapoglu and Mustafa Altun
appeared in: arXiv, 1805.06262, 2018.

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Paper

title: Sampling Based Random Number Generator for Stochastic Computing
authors: Burak Karadeniz and Mustafa Altun
presented at: IEEE International Conference on Electronics Circuits and Systems (ICECS), Batumi, Georgia, 2017.

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Paper

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Slides

title: Accurate Synthesis of Arithmetic Operations with Stochastic Logic
authors: Ensar Vahapoglu and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016.

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Paper

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Poster

[edit] National Publications in Turkish

title: Random Bit Shuffling Method for Reducing Error Rates in Stochastic Computing
title (in Turkish): Stokastik Hesaplamada Hata Oranlarını Azaltmak için Rastgele Bit Karıştırma Yöntemi
authors: Serter Yavuz and Mustafa Altun
presented at: Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyum (ELECO), Bursa, Turkey, 2014.

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Paper

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Slides

[edit] Approximate Computing

title: Efficient Hardware Implementation of Artificial Neural Networks Using Approximate Multiply-Accumulate Blocks
authors: Mohammadreza Nojehdeh, Levent Aksoy, and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020.

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Paper

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Slides

title: Systematic Synthesis of Approximate Adders and Multipliers with Accurate Error Calculations
authors: Mohammadreza Nojehdeh and Mustafa Altun
appeared in: Integration, the VLSI Journal, Vol. 70, pp. 99–107, 2020.

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Paper

title: Circuit Aware Approximate System Design with Case Studies in Image Processing and Neural Networks
authors: Tuba Ayhan and Mustafa Altun
appeared in: IEEE Access, Vol. 7, pp. 4726–4734, 2019.

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Paper

title: Approximate Fully Connected Neural Network Generation
authors: Tuba Ayhan and Mustafa Altun
presented at: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Prague, Czech Republic, 2018.

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Paper

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Slides

title: A Power Efficient System Design Methodology Employing Approximate Arithmetic Units
authors: Tuba Ayhan, Firat Kula, and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, 2017.

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Paper

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Slides

[edit] National Publications in Turkish

title: Approximate Implementation of FIR Filters on FPGA
title (in Turkish): FPGA Üzerinde Yaklaşık FIR Süzgeç Tasarımı
authors: Firat Kula, Tuba Ayhan, and Mustafa Altun
presented at: Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU), Izmir, Turkey, 2018.

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Paper

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Slides

[edit] Large-Area Electronics

[edit] Transistor Fabrication

title: Investigation of P3HT:WO3 Hybrid Electrochromic Thin Films Prepared by Solution Blending Doping
authors: Beyza Yedikardes, Mustafa Altun, and Esra Zayim
appeared in: Synthetic Metals, Vol. 297, Article 117407, 2023.

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Paper

title: Improving Threshold Voltage and ON/OFF Current Ratio of Single-Walled Carbon Nanotube Field-Effect Transistor by Post-Sonication Treatments

authors: Fereshteh Ordokhani, Beyza Yedikardes, Ece Kurt, Nihat Akkan, Nilgün Yavuz, Esra Zayim, and Mustafa Altun
appeared in: Thin Solid Films, Vol. 727, Article 138677, 2021.

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Paper

title: Enhanced Electrical Properties of P3HT:WO3 Hybrid Thin Film Transistors
authors: Beyza Yedikardes, Fereshteh Ordokhani, Nihat Akkan, Ece Kurt, Esra Zayim, Nilgün Yavuz, and Mustafa Altun
appeared in: Journal of Electronic Materials, Vol. 50, Issue 4, pp. 2466–2475, 2021.
presented at: International Conference on Advanced Nanomaterials (ANM), Aveiro, Portugal, 2019.

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Paper

PPT.jpg
Slides

[edit] Organic Transistor Modeling

title: Behavioral Modeling for Low-Voltage Pentacene-Based OTFTs and Their Implementations for Organic Logic Circuits

authors: Nihat Akkan, Mustafa Altun, and Herman Sedef
appeared in: Engineering Science and Technology, an International Journal, Vol. 37, Article 101317, 2023.

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Paper

title: The Level 3 Based SPICE Model for Low-Voltage Pentacene Thin Film Transistors
authors: Nihat Akkan, Mustafa Altun, and Herman Sedef
presented at: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Sardinia, Italy, 2022.

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Paper

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Slides

title: Modeling and Parameter Extraction of OFET Compact Models Using Metaheuristics-Based Approach

authors: Nihat Akkan, Mustafa Altun, and Herman Sedef
appeared in: IEEE Access, Vol. 7, pp. 180438–180450, 2019.

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Paper

title: Parameter Extraction Method Using Hybrid Artificial Bee Colony Algorithm for an OFET Compact Model
authors: Nihat Akkan, Mustafa Altun, and Herman Sedef
presented at: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Prague, Czech Republic, 2018.

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Paper

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[edit] Reversible Computing

[edit] CMOS Fault Tolerance

title: Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates

authors: Sajjad Parvin and Mustafa Altun
appeared in: IEEE Access, Vol. 7, pp. 163939–163947, 2019.

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Paper

title: Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates
authors: Sajjad Parvin and Mustafa Altun
presented at: IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes Island, Greece, 2019.

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Paper

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Poster

title: Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits

authors: Mustafa Altun, Sajjad Parvin, and Husrev Cilasun
appeared in: IEEE Access, Vol. 6, pp. 74475–74484, 2018.

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Paper

title: A Novel Reversible Fault Tolerant Microprocessor Design in AMS 0.35um Process

authors: Husrev Cilasun and Mustafa Altun
appeared in: Istanbul University - Journal of Electrical & Electronics Engineering, Vol. 17, No. 1, pp. 3147–3154, 2017.

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Paper

[edit] Logic Synthesis

title: Fast Synthesis of Reversible Circuits using a Sorting Algorithm and Optimization
authors: Omercan Susam and Mustafa Altun
appeared in: Journal of Multiple-Valued Logic and Soft Computing, Vol. 29, Issue 1-2, pp. 1–23, 2017.

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Paper

title: An Efficient Algorithm to Synthesize Quantum Circuits and Optimization
authors: Omercan Susam and Mustafa Altun
presented at: IEEE International Conference on Electronics Circuits and Systems (ICECS), Marseille, France, 2014.

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Paper

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[edit] National Publications in Turkish

title: Kuantum Devre Sentezi ve Optimizasyonu için Verimli bir Algoritma
authors: Omercan Susam and Mustafa Altun
presented at: Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO), Bursa, Turkey, 2014.

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Paper

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[edit] Reliability of Electronic Products

title: Distinct Degradation Processes in ZnO Varistors: Reliability Analysis and Modeling with Accelerated AC Tests
authors: Hadi Yadavari and Mustafa Altun
appeared in: Turkish Journal of Electrical Engineering and Computer Sciences, Vol. 25, No. 4, pp. 3240–3252, 2017.

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Paper

title: A Change-Point based Reliability Prediction Model using Field Return Data
authors: Mustafa Altun and Vehbi Comert
appeared in: Reliability Engineering and System Safety, Vol. 156, pp. 175–184, 2016.

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Paper

title: Effects of ZnO Varistor Degradation on the Overvoltage Protection Mechanism of Electronic Boards
authors: Hadi Yadavari, Burak Sal, Mustafa Altun, Ertunc Erturk, and Baris Ocak
presented at: European Safety and Reliability Conference (ESREL), Zurich, Switzerland, 2015.

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title: Extensive Investigation of Calibrated Accelerated Life Testing (CALT) in Comparison with Classical Accelerated Life Testing (ALT)
authors: Burak Sal and Mustafa Altun
presented at: European Safety and Reliability Conference (ESREL), Zurich, Switzerland, 2015.

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title: Warranty Forecasting of Electronic Boards using Short-term Field Data
authors: Vehbi Comert, Mustafa Altun, Mustafa Nadar, and Ertunc Erturk
presented at: Reliability and Maintainability Symposium (RAMS), Palm Harbor, USA, 2015.

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Paper

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Slides

title: Reliability Prediction of Electronic Boards by Analyzing Field Return Data
authors: Vehbi Comert, Hadi Yadavari, Mustafa Altun, and Ertunc Erturk
presented at: European Safety and Reliability Conference (ESREL), Wroclaw, Poland, 2014.

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[edit] National Publications in Turkish

title: A New Reliability Model for MOSFET Gate Oxide Breakdown
title (in Turkish): MOSFET Geçit Oksidi Kırılması için Yeni Bir Güvenilirlik Modeli
authors: Hasan Avci and Mustafa Altun
presented at: Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO), Bursa, Turkey, 2018.

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[edit] Analog Circuit Design

title: Low Input Resistance Current Buffer Stage Using a Controllable Positive Feedback Loop, and Applications of Current Conveyor Based Filters
authors: Dogus Gungordu, Mustafa Altun, and Ismail Cevik
appeared  in: AEU International Journal of Electronics and Communications, Vol. 82, pp. 58–65, 2017.

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Paper

title: Design of Positive Feedback Driven Current-Mode Amplifiers Z-Copy CDBA and CDTA and Filter Applications
authors: Ersin Alaybeyoglu, Arda Guney, Mustafa Altun, and Hakan Kuntman
appeared  in: Analog Integrated Circuits and Signal Processing, Vol. 81, Issue 1, pp. 109–120, 2014.

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Paper

title: Realisation of nth Order Current Transfer Function Employing ECCIIs and Application Examples
authors: Mustafa Altun, Hakan Kuntman, Shahram Minaei, and Onur Sayin
appeared  in: International Journal of Electronics, Vol. 96, Issue 11, pp. 1115–1126, 2009.

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Paper

title: Design of a Fully Differential Current Mode Operational Amplifier with Improved Input-Output Impedances and its Filter Applications
authors: Mustafa Altun and Hakan Kuntman
appeared  in: AEU International Journal of Electronics and Communications, Vol. 62, Issue 3, pp. 39–44, 2008.

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Paper

title: A High Drive Fully Differential Current Mode Operational Amplifier Providing High Output Impedance and Filter Application
authors: Mustafa Altun and Hakan Kuntman
presented  at: International Conference on Electrical and Electronics Engineering (ELECO), Bursa, Turkey, 2007.

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Paper

title: High CMRR Current Mode Operational Amplifier with a Novel Class AB Input Stage
authors: Mustafa Altun and Hakan Kuntman
presented  at: ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa, Italy, 2007.

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Paper

title: A Wideband CMOS Current Mode Operational Amplifier and its Use for Band Pass Filter Realization
authors: Mustafa Altun and Hakan Kuntman
presented  at: Applied Electronics (AE), Pilsen, Czech Republic, 2006.

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[edit] National Publications in Turkish

title: Yüksek Başarımlı Tümüyle Farksal Akım Modlu İşlemsel Kuvvetlendirici (COA) Tasarımı ve Tüm Geçiren Süzgeç Yapısında Kullanımı
authors: Mustafa Altun and Hakan Kuntman
presented at: Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO), Bursa, Turkey, 2006.

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Paper

title: Akım Modlu İşlemsel Kuvvetlendirici Tasarımı ve Uygulamaları
title: Design of a Current Mode Operational Amplifier and Its Applications
author: Mustafa Altun
thesis: MSc, Electronics Engineering, Istanbul Technical University, 2007.

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Thesis

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Slides

[edit] Discrete Mathematics

title: A Study on Monotone Self-dual Boolean Functions
authors: Mustafa Altun and Marc Riedel
appeared  in: Acta Mathematicae Applicatae Sinica - English Series, Vol. 33, Issue 1, pp. 43–52, 2017.

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Paper

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