EEF 205E
From The Emerging Circuits and Computation Group at ITU
(Difference between revisions)
(→Syllabus) |
(→Syllabus) |
||
(4 intermediate revisions by one user not shown) | |||
Line 2: | Line 2: | ||
== Announcements == | == Announcements == | ||
− | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Oct. | + | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Oct. 16th</span> The class is given in the room '''5204''' (second floor), EEF. |
== Syllabus == | == Syllabus == | ||
− | <div style="font-size: 120%;"> '''EEF 205E: Introduction to Logic Design''', CRN: 15211, Fridays 8:30-11:30, Room: | + | <div style="font-size: 120%;"> '''EEF 205E: Introduction to Logic Design''', CRN: 15211, Fridays 8:30-11:30, Room: 5204 (EEF), Fall 2023. </div> |
{| border="1" cellspacing="0" cellpadding="5" " width="80%" | {| border="1" cellspacing="0" cellpadding="5" " width="80%" | ||
Line 19: | Line 19: | ||
| <div style="font-size: 120%;"> '''Teaching Assistant'''</div> | | <div style="font-size: 120%;"> '''Teaching Assistant'''</div> | ||
|| | || | ||
− | + | İrem Cömertoğlu | |
− | * Email: | + | * Email: comertoglu17@itu.edu.tr |
− | * Room: | + | * Room: 3101 EEF |
|- | |- | ||
| <div style="font-size: 120%;"> '''Grading'''</div> | | <div style="font-size: 120%;"> '''Grading'''</div> | ||
Line 30: | Line 30: | ||
* Midterm Exams: '''50%''' | * Midterm Exams: '''50%''' | ||
− | ** 2 midterms ( | + | ** 2 midterms (25% each) during the lecture time that will on '''17/11/2023''' and '''22/12/2023'''. |
* Final Exam: '''40%''' | * Final Exam: '''40%''' | ||
Line 96: | Line 96: | ||
== Course Materials == | == Course Materials == | ||
− | + | Shared through Ninova. | |
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + |
Revision as of 15:53, 16 October 2023
Contents |
Announcements
- Oct. 16th The class is given in the room 5204 (second floor), EEF.
Syllabus
EEF 205E: Introduction to Logic Design, CRN: 15211, Fridays 8:30-11:30, Room: 5204 (EEF), Fall 2023.
Instructor
|
|
Teaching Assistant
|
İrem Cömertoğlu
|
Grading
|
|
Textbook
|
|
Reference Books
|
|
Policies
|
|
Weekly Course Plan
Date
|
Topic
|
Week 1, 6/10/2023 | Introduction |
Week 2, 13/10/2023 | Digital logic fundamentals: gates, combinational circuits, Boolean expressions |
Week 3, 20/10/2023 | Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares" |
Weeks 4, 27/10/2023 | Logic minimization: Karnaugh maps, Quine-McCluskey method |
Weeks 5, 3/11/2023 | Logic minimization: Karnaugh maps, Quine-McCluskey method |
Week 6, 10/11/2023 | Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.) |
Weeks 7, 17/11/2023 | MIDTERM I |
Week 8, 24/11/2023 | Combinational circuit design: implementing Boolean and arithmetic operations |
Week 9, 1/12/2023 | Area-Delay Performance analysis of combinational circuits |
Weeks 10, 8/12/2023 | Sequential circuits: latches & flip-flops |
Week 11, 15/12/2023 | Sequential circuit design: state graphs and tables, modules |
Week 12, 22/12/2023 | MIDTERM II |
Weeks 13, 29/12/2023 | Sequential circuit design: modules, state machines |
Weeks 14, 5/1/2024 | Sequential circuit design: modules, state machines |
Course Materials
Shared through Ninova.