EEF 205E
From The Emerging Circuits and Computation Group at ITU
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== Announcements == | == Announcements == | ||
− | + | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Oct. 16th</span> The class is given in the room '''5204''' (second floor), EEF. | |
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− | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Oct. | + | |
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== Syllabus == | == Syllabus == | ||
− | <div style="font-size: 120%;"> ''' | + | <div style="font-size: 120%;"> '''EEF 205E: Introduction to Logic Design''', CRN: 15211, Fridays 8:30-11:30, Room: 5204 (EEF), Fall 2023. </div> |
{| border="1" cellspacing="0" cellpadding="5" " width="80%" | {| border="1" cellspacing="0" cellpadding="5" " width="80%" | ||
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| <div style="font-size: 120%;"> '''Teaching Assistant'''</div> | | <div style="font-size: 120%;"> '''Teaching Assistant'''</div> | ||
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− | + | İrem Cömertoğlu | |
− | * Email: | + | * Email: comertoglu17@itu.edu.tr |
− | * Room: | + | * Room: 3101 EEF |
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| <div style="font-size: 120%;"> '''Grading'''</div> | | <div style="font-size: 120%;"> '''Grading'''</div> | ||
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* Homeworks: '''10%''' | * Homeworks: '''10%''' | ||
** 4 homeworks (2.5% each) | ** 4 homeworks (2.5% each) | ||
− | * Midterm Exams: ''' | + | * Midterm Exams: '''50%''' |
− | ** 2 midterms ( | + | ** 2 midterms (25% each) during the lecture time that will on '''17/11/2023''' and '''22/12/2023'''. |
* Final Exam: '''40%''' | * Final Exam: '''40%''' | ||
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* Homeworks are due at the beginning of class. Late homeworks will be downgraded by '''20%''' for each day passed the due date. | * Homeworks are due at the beginning of class. Late homeworks will be downgraded by '''20%''' for each day passed the due date. | ||
* Exams are in '''closed-notes''' and '''closed-books''' format. | * Exams are in '''closed-notes''' and '''closed-books''' format. | ||
− | * To be eligible of taking the final or the resit exam, | + | * To be eligible of taking the final or the resit exam, your average, excluding the final, should be at least '''40%''' of the class average. |
+ | * To pass the class, your overall average should be at least '''50%''' of the class average. | ||
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|| <div style="font-size: 120%;"> '''Topic'''</div> | || <div style="font-size: 120%;"> '''Topic'''</div> | ||
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− | | Week 1, | + | | Week 1, 6/10/2023 || Introduction |
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− | | Week 2, | + | | Week 2, 13/10/2023 || Digital logic fundamentals: gates, combinational circuits, Boolean expressions |
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− | | Week 3, | + | | Week 3, 20/10/2023 || Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares" |
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− | | Weeks 4, | + | | Weeks 4, 27/10/2023 || Logic minimization: Karnaugh maps, Quine-McCluskey method |
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− | | Weeks 5, | + | | Weeks 5, 3/11/2023 || Logic minimization: Karnaugh maps, Quine-McCluskey method |
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− | | Week 6, | + | | Week 6, 10/11/2023 || Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.) |
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− | | Weeks 7, | + | | Weeks 7, 17/11/2023 || MIDTERM I |
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− | | Week 8, | + | | Week 8, 24/11/2023 || Combinational circuit design: implementing Boolean and arithmetic operations |
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− | | Week 9, | + | | Week 9, 1/12/2023 || Area-Delay Performance analysis of combinational circuits |
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− | | Weeks 10, | + | | Weeks 10, 8/12/2023 || Sequential circuits: latches & flip-flops |
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− | | Week 11, | + | | Week 11, 15/12/2023 || Sequential circuit design: state graphs and tables, modules |
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− | | Week 12, | + | | Week 12, 22/12/2023 || MIDTERM II |
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− | | Weeks 13, | + | | Weeks 13, 29/12/2023 || Sequential circuit design: modules, state machines |
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− | | Weeks 14, | + | | Weeks 14, 5/1/2024 || Sequential circuit design: modules, state machines |
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== Course Materials == | == Course Materials == | ||
− | + | Shared through Ninova. | |
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Latest revision as of 15:53, 16 October 2023
Contents |
[edit] Announcements
- Oct. 16th The class is given in the room 5204 (second floor), EEF.
[edit] Syllabus
EEF 205E: Introduction to Logic Design, CRN: 15211, Fridays 8:30-11:30, Room: 5204 (EEF), Fall 2023.
Instructor
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Teaching Assistant
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İrem Cömertoğlu
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Grading
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Textbook
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Reference Books
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Policies
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[edit] Weekly Course Plan
Date
|
Topic
|
Week 1, 6/10/2023 | Introduction |
Week 2, 13/10/2023 | Digital logic fundamentals: gates, combinational circuits, Boolean expressions |
Week 3, 20/10/2023 | Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares" |
Weeks 4, 27/10/2023 | Logic minimization: Karnaugh maps, Quine-McCluskey method |
Weeks 5, 3/11/2023 | Logic minimization: Karnaugh maps, Quine-McCluskey method |
Week 6, 10/11/2023 | Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.) |
Weeks 7, 17/11/2023 | MIDTERM I |
Week 8, 24/11/2023 | Combinational circuit design: implementing Boolean and arithmetic operations |
Week 9, 1/12/2023 | Area-Delay Performance analysis of combinational circuits |
Weeks 10, 8/12/2023 | Sequential circuits: latches & flip-flops |
Week 11, 15/12/2023 | Sequential circuit design: state graphs and tables, modules |
Week 12, 22/12/2023 | MIDTERM II |
Weeks 13, 29/12/2023 | Sequential circuit design: modules, state machines |
Weeks 14, 5/1/2024 | Sequential circuit design: modules, state machines |
[edit] Course Materials
Shared through Ninova.