EEF 205E

From The Emerging Circuits and Computation Group at ITU
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|  Week  1, 8/10/2021       || Introduction
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|  Week  1, 6/10/2023       || Introduction
 
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|  Week  2, 15/10/2021       || Digital logic fundamentals: gates, combinational circuits, Boolean expressions
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|  Week  2, 13/10/2023       || Digital logic fundamentals: gates, combinational circuits, Boolean expressions
 
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|  Week  3, 22/10/2021       || Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
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|  Week  3, 20/10/2023       || Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
 
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|  Weeks 4, 29/10/2021 || HOLIDAY!
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|  Weeks 4, 27/10/2023 || Logic minimization: Karnaugh maps, Quine-McCluskey method
 
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|  Weeks 5, 5/11/2021   || Logic minimization: Karnaugh maps, Quine-McCluskey method
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|  Weeks 5, 3/11/2023   || Logic minimization: Karnaugh maps, Quine-McCluskey method
 
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|  Week 6, 12/11/2021     || Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
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|  Week 6, 10/11/2023     || Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
 
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|  Weeks 7, 19/11/2021 || MIDTERM I
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|  Weeks 7, 17/11/2023 || MIDTERM I
 
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|  Week  8, 26/11/2021   || HOLIDAY, no class
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|  Week  8, 24/11/2023   || Combinational circuit design: implementing Boolean and arithmetic operations
 
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|  Week  9, 3/12/2021     || Combinational circuit design: implementing Boolean and arithmetic operations
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|  Week  9, 1/12/2023     || Area-Delay Performance analysis of combinational circuits
 
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|  Weeks 10, 10/12/2021 || Area-Delay Performance analysis of combinational circuits
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|  Weeks 10, 8/12/2023 || Sequential circuits: latches & flip-flops
 
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|  Week  11, 17/12/2021     || Sequential circuits: latches & flip-flops
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|  Week  11, 15/12/2023     || Sequential circuit design: state graphs and tables, modules
 
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|  Week  12, 24/12/2021   || MIDTERM II
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|  Week  12, 22/12/2023   || MIDTERM II
 
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|  Weeks 13, 31/12/2021 || Sequential circuit design: state graphs and tables, modules
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|  Weeks 13, 29/12/2023 || Sequential circuit design: modules, state machines
 
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|  Weeks 14, 7/1/2022 || Sequential circuit design: modules, state machines
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|  Weeks 14, 5/1/2024 || Sequential circuit design: modules, state machines
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|  Weeks 15, 14/1/2022 || Sequential circuit design: modules, state machines
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Revision as of 13:00, 4 October 2023

Contents

Announcements

  • Oct. 4th The class is given in the room 6309 (third floor), EEF.

Syllabus

EEF 205E: Introduction to Logic Design, CRN: 15211, Fridays 8:30-11:30, Room: 6309 (EEF), Fall 2023.
Instructor

Mustafa Altun

  • Email: altunmus@itu.edu.tr
  • Tel: 02122856635
  • Office hours: 15:00 – 16:00 on Wednesdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant

Emre Altuner

  • Email: altuner16@itu.edu.tr
  • Room: 3107 EEF
Grading
  • Homeworks: 10%
    • 4 homeworks (2.5% each)
  • Midterm Exams: 50%
    • 2 midterms (20% each) during the lecture time that will on 19/11/2021 and 24/12/2021.
  • Final Exam: 40%
Textbook
  • Wakerly, J. F. (20XX). Digital Design Principles & Practices. Prentice Hall.
Reference Books
  • Roth Jr, C., & Kinney, L. (20XX). Fundamentals of logic design. Cengage Learning.
  • Mano, M. M., & Kime, C. R. (20XX). Logic and Computer Design Fundamentals. Prentice Hall.
Policies
  • Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date.
  • Exams are in closed-notes and closed-books format.
  • To be eligible of taking the final or the resit exam, your average, excluding the final, should be at least 40% of the class average.
  • To pass the class, your overall average should be at least 50% of the class average.

Weekly Course Plan

Date
Topic
Week 1, 6/10/2023 Introduction
Week 2, 13/10/2023 Digital logic fundamentals: gates, combinational circuits, Boolean expressions
Week 3, 20/10/2023 Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
Weeks 4, 27/10/2023 Logic minimization: Karnaugh maps, Quine-McCluskey method
Weeks 5, 3/11/2023 Logic minimization: Karnaugh maps, Quine-McCluskey method
Week 6, 10/11/2023 Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
Weeks 7, 17/11/2023 MIDTERM I
Week 8, 24/11/2023 Combinational circuit design: implementing Boolean and arithmetic operations
Week 9, 1/12/2023 Area-Delay Performance analysis of combinational circuits
Weeks 10, 8/12/2023 Sequential circuits: latches & flip-flops
Week 11, 15/12/2023 Sequential circuit design: state graphs and tables, modules
Week 12, 22/12/2023 MIDTERM II
Weeks 13, 29/12/2023 Sequential circuit design: modules, state machines
Weeks 14, 5/1/2024 Sequential circuit design: modules, state machines

Course Materials

Homeworks & Solutions Homeworks & Solutions Quizzes & Solutions Sample Problems & Solutions Exams
Homework 1 & Solutions Homework 3 & Solutions Quiz 1 & Solutions Problem Set 1 & Solutions Midterm 1 & Solutions
Homework 2 Homework 4 & Solutions Quiz 2 & Solutions Problem Set 2 & Solutions Midterm 2 & Solutions
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