Research

Computing with Nano-Crossbar Arrays

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures. Computing with crossbar arrays is achieved by its crosspoints behaving as switches, either two-terminal or four-terminal. Depending on the technology used, a two-terminal switch behaves as a diode, a resistive/memristive switch, or a field effect transistor (FET). On the other hand, a four-terminal switch has a unique behavior. While there have been many different technologies proposed for two-terminal switch based arrays, technology development for four-terminal switch based arrays, called switching lattices, has recently started.

For both two-terminal and four-terminal switch based arrays, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. We also aim to develeop CMOS-compatible technologies for crossbar arrays, specifically for switching lattices.

Technology Development

Although a four-terminal switch based array offers a significant area advantage, in terms of the number of switches, compared to the ones having two-terminal switches, its realization at the technology level needs further justifications and raises a number of questions about its feasibility. We answer these questions. First, by using three dimensional technology computer-aided design (TCAD) simulations, we show that four-terminal switches can be directly implemented with the CMOS technology. For this purpose, we try different semiconductor gate materials in different formations of geometric shapes. Then, by fitting the TCAD simulation data to the standard CMOS current-voltage equations, we develop a Spice model of a four-terminal switch. Finally, we successfully perform Spice circuit simulations on four-terminal switches with different sizes.

Performance Optimization

We study crossbar arrys including the memristive ones. We propose a defect-tolerant logic synthesis algorithms by considering area, delay, and power costs of the arrays.

Fault Tolerance

We examine reconfigurable crossbar arrays by considering randomly occurred stuck-open and stuck-closed crosspoint faults. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions.

Synthesis

We study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a diode, a FET, and a four-terminal switch. For these three types, we give array size formulations for a given Boolean function. Additionally, we focus on four-terminal switch based implementations and propose an algorithm that implements Boolean functions with optimal array sizes.

Reversible Computing

Unlike conventional CMOS circuits, reversible circuits do not have latent faults, so faults occurring in internal circuit nodes always result in an error at the output. This is a unique feature for online or concurrent fault tolerance. Motivated by this, we implement error tolerant CMOS circuit blocks by exploiting reversible computing. We first synthesize reversible circuits with reversible gates; then we make them fault-tolerant; and finally we perform conversion from reversible gates to CMOS gates.

Perfect Online Error Detection

In order to achieve a CMOS circuit having 100% online or concurrent error detection, we exploit reversible computing by proposing a new, fault preservative, and reversible gate library. We ensure that the parity, even or odd, is preserved at all levels including the output level unless there is a faulty node.

Online Error Detection and Correction

We develop two techniques to make a reversible circuit fault-tolerant by using multiple-control Toffoli gates. The first technique is based on single parity preserving, and offers error detection for odd number of errors at the output. The second technique is constructed on Hamming codes for error correction. We also claim that perfect error detection is possible with conservative reversible gates such as a Fredkin gate. As the next step, we utilize the proposed reversible circuits with conventional CMOS gates.

Stochastic and Bit Stream Computing

We propose a novel computing paradigm “Bit Stream Computing (BSC)” that does not necessarily employ randomly or Binomially distributed bit streams as stochastic computing does. Any type of streams can be used either stochastic or deterministic. The proposed paradigm benefits from the area advantage of stochastic logic and the accuracy advantage of conventional binary logic. We implement accurate arithmetic multiplier and adder circuits, classified as asynchronous or synchronous. We believe that this study opens up new horizons for computing that enables us to implement much smaller yet accurate arithmetic circuits compared to the conventional binary and stochastic ones.

Approximate Circuit and System Design

Power/Area Efficient Approximate System Design Methodology

This work provides power/area efficiency of circuit-level design with accuracy supervision of system-level design. The proposed method selects approximate computational units that minimize the total computation cost, yet maintaining the ultimate performance. The method investigates the overall system from the highest level down to the arithmetic units to determine the sufficient output quality at each block.

Reliability of Electronic Products

The rapid developments in electronics, especially in the last decade, have elevated the importance of electronics reliability. Conventionally used accelerated reliability tests have lost their significance; time consuming and expensive feature of these tests is against the demands of today's very rapid electronic product cycles. In this study, we propose less costly, yet accurate, reliability prediction techniques using field return data, new accelerated test methodologies, and physics of failure based simulations. We cooperate with one of the Europe’s largest household appliance companies Arçelik A.Ş..

Reliability Analysis and Prediction with Field Data

We propose an accurate reliability prediction model for high-volume electronic products throughout their warranty periods by using field return data. Our model is constructed on a Weibull-exponential hazard rate scheme by using the proposed change point detection method based on backward and forward data analysis. Our prediction model can make a 36-month (full warranty) reliability prediction of an electronic board with using its field data as short as 3 months.

Degradation Processes in Varistors

We investigate different degradation mechanisms of ZnO varistors. We propose a model showing how the varistor voltage Vv changes by time for different stress levels. For this purpose, accelerated degradation tests are applied for different AC current levels; then voltage values are measured. Different from the common practice in the literature that considers a degradation with only decreasing Vv values, we demonstrate either an increasing or a decreasing trend in the Vv parameter.

Calibrated Accelerated Life Testing

Dramatic decrease in failure rates for electronic products makes conventional accelerated life tests (ALT) extremely time consuming and costly. Recently proposed calibrated accelerated life tests (CALT) aim to use fewer samples than those used in ALT. We thoroughly compare ALT and CALT by considering the effects of failure rate, acceleration factor, and stress level on the required test time.

Analog Circuit Design

Positive Feedback

The conventional wisdom is that analog circuits should not include positive feedback loops. As controversial as it seems, we have successfully used positive feedback for impedance improvement in a current amplifier. With adding few transistors we have achieved very low input resistance values. Additionally, we have proposed a new fully-differential current amplifier and tested it in a filter application.

Discrete Mathematics

Self Duality Problem

The problem of testing whether a monotone Boolean function in irredundant disjuntive normal form (IDNF) is self-dual is one of few problems in circuit/time complexity whose precise tractability status is unknown. We have focused on this famous problem. We have shown that monotone self-dual Boolean functions in IDNF do not have more variables than disjuncts. We have proposed an algorithm to test whether a monotone Boolean function in IDNF with n variables and n disjuncts is self-dual. The algorithm runs in O(n^3) time.