Research

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Our research is multidisciplinary and spans areas such as circuit design, emerging computing models, and mathematics. Our main goal is developing novel ways of computing for nanoscale technologies.
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Our research aims to develop novel ways of computing, circuit design, and reliability for electronic circuits and systems. Our research mainly targets future and emerging technologies.
  
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== Computing with Networks of Nanoswitches ==
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<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Computing with Switching Nano Arrays </h2>
  
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As current CMOS-based technology is approaching its anticipated limits, research is shifting to novel forms of nanoscale technologies including molecular-scale self-assembled systems. Unlike conventional CMOS that can be patterned in complex ways with lithography, self-assembled nanoscale systems generally consist of regular structures. Logical functions are achieved with crossbar-type switches. Our model, a network of four- terminal switches, corresponds to this type of switch in a variety of emerging technologies, including nanowire crossbar arrays and magnetic switch-based structures.
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=== Synthesis Problem ===
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As current CMOS-based technology is approaching its anticipated limits, research is shifting to novel forms of nanoscale technologies including molecular-scale self-assembled systems. Unlike conventional CMOS that can be patterned in complex ways with lithography, self-assembled nanoscale systems generally consist of regular structures. Logical functions are achieved with crossbar-type switches. Our model, a network of four- terminal switches, corresponds to this type of switch in a variety of emerging technologies, including nanowire crossbar arrays and magnetic switch-based structures.
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In his seminal Master's Thesis, [http://en.wikipedia.org/wiki/Claude_Shannon Claude Shannon] made the connection between Boolean algebra and switching circuits. He considered '''two-terminal''' switches corresponding to electromagnetic relays. A Boolean function can be implemented in terms of connectivity across a network of switches, often arranged in a series/parallel configuration. We have developed a method for synthesizing Boolean functions with networks of '''four-terminal switches''', arranged in rectangular lattices.
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 +
<h3>
 +
Synthesis</h3>
 +
In his seminal Master's Thesis, [http://en.wikipedia.org/wiki/Claude_Shannon Claude Shannon] made the connection between Boolean algebra and switching circuits. He considered '''two-terminal''' switching networks to implement any Boolean function that is the foundation of CMOS circuit design techniques. In this work, we have considered '''four-terminal''' switching networks to implement any Boolean function that aims to be a foundation of nano array based circuit design techniques.
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[[Image:Research-1.png|center|none|800px|link=]]
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 +
<h3>
 +
Reliability</h3>
 +
 
 +
We have devised a novel framework for digital computation with networks of nanoscale switches with high defect rates, based on the mathematical phenomenon of [http://en.wikipedia.org/wiki/Percolation_theory percolation]. With random connectivity, percolation gives rise to a '''sharp non-linearity''' in the probability of global connectivity as a function of the probability of local connectivity. This phenomenon is exploited to compute Boolean functions robustly, in the presence of random defects.
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[[Image:Research-2.png|center|none|800px|link=]]
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[[Image:2-switch.png|center|thumb|none|400px|link=|Shannon's model: '''two-terminal switches'''.  Each switch is either ON (closed) or OFF (open). A Boolean function is implemented in terms of connectivity across a network of switches, arranged in a series/parallel configuration. This network implements the function f = x_1 x_2 x_3 + x_1 x _2 x_5 x_6 + x_4 x_5 x_2 x_3 + x_4
 
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x_5 x_6.]]
 
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|| &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 
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|| [[Image:4-switch.png|center|thumb|none|375px|link=|Our model: '''four-terminal switches'''. Each switch is either mutually connected to its neighbors (ON) or disconnected (OFF).  A Boolean function is implemented in terms of connectivity between the top and bottom plates. This network implements the same function, f = x_1 x_2 x_3 + x_1 x _2 x_5 x_6 + x_4 x_5 x_2 x_3 + x_4
 
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x_5 x_6.]]
 
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| width="696" |'''Selected Publication'''
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| width="696" |'''Selected Publications'''
 
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| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
 
| [http://www.dac.com Design Automation Conference], Anaheim, CA, 2010.
 
| [http://www.dac.com Design Automation Conference], Anaheim, CA, 2010.
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|- valign="top"
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| '''presented&nbsp;at''':
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| [http://fias.uni-frankfurt.de/ International Conference on Computational Modelling of <br> Nanostructured Materials (ICCMNM)-FIAS], Frankfurt, Germany, 2013.
 
|}
 
|}
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| align=center width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
 
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/ca/Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf]]</span>
 
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/ca/Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf]]</span>
 
<br>
 
<br>
 
[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Paper]]
 
[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Paper]]
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<span class="plainlinks">
  
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=== Robust Computation ===
 
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We have devised a novel framework for digital computation with lattices of nanoscale switches with high defect rates, based on the mathematical phenomenon of [http://en.wikipedia.org/wiki/Percolation_theory percolation]. With random connectivity, percolation gives rise to a sharp non-linearity in the probability of global connectivity as a function of the probability of local connectivity. This phenomenon is exploited to compute Boolean functions robustly, in the presence of defects.
 
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−
[[Image:Lattice-defects-percolation.jpg|left|thumb|none|900px|link=|In a switching network with defects, percolation can be exploited to produce robust Boolean functionality. Unless the defect rate exceeds an error margin, with high probability no connection forms between the top and bottom plates for logical zero ("OFF"); with high probability, a connection forms for logical one ("ON").]]
 
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| width="696" |'''Selected Publication'''
 
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{| style="border:1px solid #abd5f5; background:#f1f5fc;"
  
 
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| align=center width="70" |  
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| align=center width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
 
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/3b/Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf]]</span>
 
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/3b/Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf]]</span>
 
<br>
 
<br>
 
[[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Paper]]
 
[[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Paper]]
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== Mathematics ==
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{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
  
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=== Self-Duality Problem ===
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|- valign=top
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| width="696" |'''Funding Projects'''
 +
|}
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{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
  
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The problem of testing whether a monotone Boolean function in irredundant disjuntive normal form (IDNF) is self-dual is one of few problems in circuit complexity whose precise tractability status is '''unknown'''. We have focused on this '''famous problem'''. We have shown that monotone self-dual Boolean functions in IDNF do not have more variables than disjuncts. We have proposed an algorithm to test whether a monotone Boolean function in IDNF with ''n'' variables and ''n'' disjuncts is self-dual. The algorithm runs in O(n^4) time.
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|
 +
{|
 +
|- valign=top
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| width="140" |'''title''':
 +
| width="558"|Synthesis and Reliability Analysis of Nano Switching Arrays
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|- valign="top"
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| '''agency & program''':
 +
| [http://www.tubitak.gov.tr/tr/destekler/akademik/ulusal-destek-programlari/icerik-3501-ulusal-genc-arastirmaci-kariyer-gelistirme-programi TUBITAK Career Program (3501)]
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|- valign="top"
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| '''duration''':
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| 2014-2017
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|}
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 +
|}
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{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
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 +
|
 +
{|
 +
|- valign="top"
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| width="140" |'''title''':
 +
| width="558"|Logic Circuit Design for Nano Arrays
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|- valign="top"
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| '''agency & program''':
 +
| [http://tubitak.gov.tr/tr/burslar/lisans/burs-programlari/2209-a TUBITAK Undergraduate Students Research Projects Support Program (2209/A)]
 +
|- valign="top"
 +
| '''duration''':
 +
| 01/2014-07/2014
 +
|}
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 +
|}
 +
 
 +
|}
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|}
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|}
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<!--        RELIABILITY    -->
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|-
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| colspan="2" style="background:#8FBCBF; text-align:center; padding:1px; border-bottom:1px #8FBCBF solid;" |
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Reliability of Electronic Boards </h2>
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|-
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| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
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The rapid developments in electronics, especially in the last decade, have initiated the inception of electronics reliability . Conventionally used accelerated reliability tests have lost their significance; time consuming and expensive feature of these tests is against the demands of today's very rapid electronic product cycles. In this study, we propose less costly, yet accurate, reliability prediction techniques using field return data, new accelerated test methodologies, and physics of failure based simulations. We cooperate with one of the Europe’s largest household appliances companies [http://www.arcelik.com.tr/default.aspx?lang=en-US Arçelik A.Ş.].
 +
 
 +
[[Image:Research-3.png|center|none|800px|link=]]
 +
 
 +
<h3>
 +
Field Data Analysis and Prediction</h3>
 +
 
 +
We perform field return data analysis of electronic boards having two steps '''filtering''' and '''modeling'''. In the first step of filtering we eliminate improper data, consisting of obvious and hidden errors, from the whole field return data. In the second step of modeling, we use the filtered data to develop our piecewise reliability model. Our reliability analysis is based on a new technique that deals with forward and backward time analysis of the data.
 +
 
 +
We precisely predict the reliability performance of electronic boards throughout the warranty period by using very '''short-term field return data'''. For electronic boards targeted in this study, warranty period is 3 years, and we use field data of 3 months.
 +
 
 +
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|
  
 
{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
 
{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
  
 
|- valign=top
 
|- valign=top
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| width="696" |'''Selected Publication'''
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| width="696" |'''Selected Publications'''
 
|}
 
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{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
  
 
|
 
|
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{|  
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{|
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
−
| width="524"|[[Media:Altun_Riedel_A_Study_on_Monotone_Self_Dual_Boolean_Functions.pdf | A Study on Monotone Self-dual Boolean Functions]]
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| width="450"|[[Media:Comert_Yadavari_Altun_Erturk_Reliability_Prediction_of_Electronic_Boards_by_Analyzing_Field_Return_Data.pdf | Reliability Prediction of Electronic Boards by Analyzing Field Return Data]]
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|- valign=top
+
|- valign="top"
 
| '''authors''':
 
| '''authors''':
−
| [[Mustafa Altun]] and [http://cadbio.com/wiki/index.php/Marc_Riedel Marc Riedel]
+
| Vehbi Comert, Hadi Yadavari, [[Mustafa Altun]], and Ertunc Erturk
 
|- valign="top"
 
|- valign="top"
−
| '''submitted &nbsp;to''':
+
| '''presented&nbsp;at''':
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| ..., 2014.
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| [http://www.esrel2014.org/ European Safety and Reliability Conference], Wroclaw ,Poland, 2014.
 
|}
 
|}
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| align=center width="70" |
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<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/d4/Comert_Yadavari_Altun_Erturk_Reliability_Prediction_of_Electronic_Boards_by_Analyzing_Field_Return_Data.pdf]]</span>
 +
<br>
 +
[[Media:Comert_Yadavari_Altun_Erturk_Reliability_Prediction_of_Electronic_Boards_by_Analyzing_Field_Return_Data.pdf | Paper]]
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| align="center" width="70" |
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<span class="plainlinks">
  
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| align=center width="70" |  
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[[File:PPT.jpg|60px|link=]]
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</span>
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<br> Slides
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{| style="border:1px solid #abd5f5; background:#f1f5fc;"
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|
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{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="450"|[[Media:Comert_Altun_Nadar_Erturk_Warranty_Forecasting_of_Electronic_Boards_using_Short-term_Field_Data.pdf | Warranty Forecasting of Electronic Boards using Short-term Field Data]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Vehbi Comert, [[Mustafa Altun]], [http://akademi.itu.edu.tr/nadar/ Mustafa Nadar], and Ertunc Erturk
 +
|- valign=top
 +
| '''accepted&nbsp;at''':
 +
| [http://rams.org/ Reliability and Maintainability Symposium], Palm Harbor, FL, 2015.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fd/Comert_Altun_Nadar_Erturk_Warranty_Forecasting_of_Electronic_Boards_using_Short-term_Field_Data.pdf]]</span>
 +
<br>
 +
[[Media:Comert_Altun_Nadar_Erturk_Warranty_Forecasting_of_Electronic_Boards_using_Short-term_Field_Data.pdf| Abstract]]
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| align="center" width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
  
−
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/53/Altun_Riedel_A_Study_on_Monotone_Self_Dual_Boolean_Functions.pdf]]</span>
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[[File:PPT.jpg|60px|link=]]
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</span>
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<br> Slides
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|}
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|}
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| style="border:1px solid transparent;" |
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<!--        PROJE      -->
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|
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{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
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 +
|- valign=top
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| width="696" |'''Funding Projects'''
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|}
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{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
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 +
|
 +
{|
 +
|- valign=top
 +
| width="140" |'''title''':
 +
| width="558"|A reliability Methodology for Appliance Electronic Cards
 +
|- valign="top"
 +
| '''agency & program''':
 +
| [http://www.tubitak.gov.tr/tr/destekler/akademik/ulusal-destek-programlari/icerik-1505-universite-sanayi-isbirligi-destek-programi TUBITAK University-Industry Collaboration Grant Program (1505)]
 +
|- valign="top"
 +
| '''duration''':
 +
| 2013-2015
 +
|}
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 +
|}
 +
{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
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 +
|
 +
{|
 +
|- valign="top"
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| width="140" |'''title''':
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| width="558"|Gate Oxide Breakdown Failure Mechanism of CMOS Transistors
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|- valign="top"
 +
| '''agency & program''':
 +
| [http://www.tubitak.gov.tr/tr/burslar/lisans/burs-programlari/icerik-2209-b-sanayi-odakli-lisans-bitirme-tezi-destekleme-programi TUBITAK Industry Oriented Senior Project Support Program (2241/A)]
 +
|- valign="top"
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| '''duration''':
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| 2013-2014
 +
|}
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|}
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|}
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|}
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|}
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<!--        QUANTUM      -->
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|-
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| colspan="2" style="background:#8FBCAF; text-align:center; padding:1px; border-bottom:1px #8FBCAF solid;" |
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Quantum Circuit Design </h2>
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|-
 +
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
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 +
<h3>
 +
Synthesis and Optimization</h3>
 +
 
 +
We propose a fast synthesis algorithm that implements any given reversible Boolean function with quantum gates. Instead of an exhaustive search on every given function, our algorithm creates a library of '''essential functions''' and performs '''sorting'''. As an example, to implement 4 bit circuits we only use 120 essential functions out of all 20922789888000 functions.
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 +
By considering the physical structure of quantum gates, we show that optimum area solutions proposed in the literature are '''not actually optimum'''; they can be improved.
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 +
[[Image:Research-4.png|center|none|800px|link=]]
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|- valign=top
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| width="696" |'''Selected Publications'''
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|}
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{| style="border:1px solid #abd5f5; background:#f1f5fc;"
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|
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{|
 +
|- valign=top
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| width="100" |'''title''':
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| width="450"|[[Media:Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pdf| An Efficient Algorithm to Synthesize Quantum Circuits and Optimization]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Ömercan Susam and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''submitted&nbsp;to''':
 +
| [http://www.ieee-icecs2014.org/ IEEE International Conference on Electronics Circuits and Systems],<br> Marseille, France, 2014.
 +
|}
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| align=center width="70" |
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<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pdf]]</span>
 
<br>
 
<br>
−
[[Media:Altun_Riedel_A_Study_on_Monotone_Self_Dual_Boolean_Functions.pdf | Paper]]
+
[[Media:Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pdf | Paper]]
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| align="center" width="70" |
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<span class="plainlinks">
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[[File:PPT.jpg|60px|link=]]
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</span>
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<br> Slides
 
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|}
  
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== Analog Circuit Design ==
+
|}
  
−
=== Positive Feedback ===
+
| style="border:1px solid transparent;" |
−
The conventional wisdom is that analog circuits should not include positive feedback loops. As controversial as it seems, we have successfully used '''positive feedback''' for impedance improvement in a current amplifier. With adding few transistors we have achieved very low input resistance values. We have tested the proposed fully-differential current amplifier in a filter application.
+
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| width="696" |'''Funding Projects'''
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|- valign=top
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| width="140" |'''title''':
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| width="558"|Quantum Circuit Design and Computation
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|- valign="top"
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| '''agency & program''':
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| [http://bap.itu.edu.tr/ Istanbul Technical University Research Support Program (ITU-BAP)]
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|- valign="top"
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| '''duration''':
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| 2014-2015
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| width="140" |'''title''':
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| width="558"|Synthesizing Quantum Circuits
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| '''agency & program''':
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| [http://tubitak.gov.tr/tr/burslar/lisansustu/egitim-burs-programlari/icerik-2211-yurt-ici-lisansustu-burs-programi TUBITAK MSc Scholarship Program in Priority Areas (2210/C)]
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|- valign="top"
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| '''duration''':
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| 2014-2015
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Analog Circuit Design </h2>
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<h3>
 +
Positive Feedback</h3>
 +
The conventional wisdom is that analog circuits should not include positive feedback loops. As controversial as it seems, we have successfully used '''positive feedback''' for impedance improvement in a current amplifier. With adding few transistors we have achieved very low input resistance values. Additionally, we have proposed a new fully-differential current amplifier and tested it in a filter application.
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|- valign=top
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| width="696" |'''Selected Publication'''
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| width="696" |'''Selected Publications'''
 
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|- valign=top
 
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| width="100" |'''title''':
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| width="524"|[[Media:Altun_Kuntman_Design_of_a_Fully_Differential_Current_Mode_Operational_Amplifier_with_its_Filter_Applications.pdf | Design of a Fully Differential Current Mode Operational Amplifier with its Filter Applications]]
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| width="450"|[[Media:Altun_Kuntman_Design_of_a_Fully_Differential_Current_Mode_Operational_Amplifier_with_its_Filter_Applications.pdf | Design of a Fully Differential Current Mode Operational Amplifier with its Filter Applications]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
 
| [[Mustafa Altun]] and [http://web.itu.edu.tr/~kuntman/ Hakan Kuntman]
 
| [[Mustafa Altun]] and [http://web.itu.edu.tr/~kuntman/ Hakan Kuntman]
 
|- valign="top"
 
|- valign="top"
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| '''appeared &nbsp;in''':
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| '''appeared&nbsp;in''':
 
| [http://www.sciencedirect.com/science/journal/14348411 AEU International Journal of Electronics and Communications], <br>Vol. 62, Issue 3, pp. 39&ndash;44, 2008.
 
| [http://www.sciencedirect.com/science/journal/14348411 AEU International Journal of Electronics and Communications], <br>Vol. 62, Issue 3, pp. 39&ndash;44, 2008.
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|- valign="top"
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| '''presented&nbsp;at''':
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| [http://www.glsvlsi.org/ ACM Great Lakes Symposium on VLSI (GLSVLSI)], Stresa, Italy, 2007.
 
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[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/ca/Altun_Kuntman_Design_of_a_Fully_Differential_Current_Mode_Operational_Amplifier_with_its_Filter_Applications.pdf]]</span>
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<br>
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[[Media:Altun_Kuntman_Design_of_a_Fully_Differential_Current_Mode_Operational_Amplifier_with_its_Filter_Applications.pdf | Paper]]
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[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e5/Altun_Kuntman_Design_of_a_Fully_Differential_Current_Mode_Operational_Amplifier_with_its_Filter_Applications.pdf]]</span>
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[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/77/Altun_Kuntman_A_Wideband_CMOS_Current-Mode_Operational_Amplifier_and_Its_Use_for_Band-Pass_Filter_Realization.ppt]]
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</span>
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<br> [http://www.ecc.itu.edu.tr/images/7/77/Altun_Kuntman_A_Wideband_CMOS_Current-Mode_Operational_Amplifier_and_Its_Use_for_Band-Pass_Filter_Realization.ppt Slides]
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Discrete Mathematics </h2>
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<h3>
 +
Self Duality Problem</h3>
 +
 
 +
The problem of testing whether a monotone Boolean function in irredundant disjuntive normal form (IDNF) is self-dual is one of few problems in circuit/time complexity whose precise tractability status is '''unknown'''. We have focused on this '''famous problem'''. We have shown that monotone self-dual Boolean functions in IDNF do not have more variables than disjuncts. We have proposed an algorithm to test whether a monotone Boolean function in IDNF with ''n'' variables and ''n'' disjuncts is self-dual. The algorithm runs in O(n^3) time.
 +
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| width="450"|[[Media:Altun_Riedel_A_Study_on_Monotone_Self_Dual_Boolean_Functions.pdf | A Study on Monotone Self-dual Boolean Functions]]
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|- valign="top"
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| [[Mustafa Altun]] and [http://cadbio.com/wiki/index.php/Marc_Riedel Marc Riedel]
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| '''submitted &nbsp;to''':
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| ..., 2014.
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[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/53/Altun_Riedel_A_Study_on_Monotone_Self_Dual_Boolean_Functions.pdf]]</span>
 
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[[Media:Altun_Kuntman_Design_of_a_Fully_Differential_Current_Mode_Operational_Amplifier_with_its_Filter_Applications.pdf | Paper]]
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</span>
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<br> [http://www.ecc.itu.edu.tr/images/1/18/Altun_Riedel_A_Study_on_Monotone_Self_Dual_Boolean_Functions.ppt Slides]
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Revision as of 21:21, 3 July 2014

Our research aims to develop novel ways of computing, circuit design, and reliability for electronic circuits and systems. Our research mainly targets future and emerging technologies.

Contents

Computing with Switching Nano Arrays

As current CMOS-based technology is approaching its anticipated limits, research is shifting to novel forms of nanoscale technologies including molecular-scale self-assembled systems. Unlike conventional CMOS that can be patterned in complex ways with lithography, self-assembled nanoscale systems generally consist of regular structures. Logical functions are achieved with crossbar-type switches. Our model, a network of four- terminal switches, corresponds to this type of switch in a variety of emerging technologies, including nanowire crossbar arrays and magnetic switch-based structures.

Synthesis

In his seminal Master's Thesis, Claude Shannon made the connection between Boolean algebra and switching circuits. He considered two-terminal switching networks to implement any Boolean function that is the foundation of CMOS circuit design techniques. In this work, we have considered four-terminal switching networks to implement any Boolean function that aims to be a foundation of nano array based circuit design techniques.

Research-1.png

Reliability

We have devised a novel framework for digital computation with networks of nanoscale switches with high defect rates, based on the mathematical phenomenon of percolation. With random connectivity, percolation gives rise to a sharp non-linearity in the probability of global connectivity as a function of the probability of local connectivity. This phenomenon is exploited to compute Boolean functions robustly, in the presence of random defects.

800px
Selected Publications
title: Logic Synthesis for Switching Lattices
authors: Mustafa Altun and Marc Riedel
appeared in: IEEE Transactions on Computers,
Vol. 61, Issue 11, pp. 1588–1600, 2012.
presented at: Design Automation Conference, Anaheim, CA, 2010.
presented at: International Conference on Computational Modelling of
Nanostructured Materials (ICCMNM)-FIAS, Frankfurt, Germany, 2013.

PDF.png
Paper

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Slides

title: Synthesizing Logic with Percolation in Nanoscale Lattices
authors: Mustafa Altun and Marc Riedel
appeared in: International Journal of Nanotechnology and Molecular Computation,
Vol. 3, Issue 2, pp. 12–30, 2011.
presented at: Design Automation Conference, San Francisco, CA, 2009.

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Paper

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Slides

Funding Projects
title: Synthesis and Reliability Analysis of Nano Switching Arrays
agency & program: TUBITAK Career Program (3501)
duration: 2014-2017
title: Logic Circuit Design for Nano Arrays
agency & program: TUBITAK Undergraduate Students Research Projects Support Program (2209/A)
duration: 01/2014-07/2014


Reliability of Electronic Boards

The rapid developments in electronics, especially in the last decade, have initiated the inception of electronics reliability . Conventionally used accelerated reliability tests have lost their significance; time consuming and expensive feature of these tests is against the demands of today's very rapid electronic product cycles. In this study, we propose less costly, yet accurate, reliability prediction techniques using field return data, new accelerated test methodologies, and physics of failure based simulations. We cooperate with one of the Europe’s largest household appliances companies Arçelik A.Ş..

Research-3.png

Field Data Analysis and Prediction

We perform field return data analysis of electronic boards having two steps filtering and modeling. In the first step of filtering we eliminate improper data, consisting of obvious and hidden errors, from the whole field return data. In the second step of modeling, we use the filtered data to develop our piecewise reliability model. Our reliability analysis is based on a new technique that deals with forward and backward time analysis of the data.

We precisely predict the reliability performance of electronic boards throughout the warranty period by using very short-term field return data. For electronic boards targeted in this study, warranty period is 3 years, and we use field data of 3 months.

Selected Publications
title: Reliability Prediction of Electronic Boards by Analyzing Field Return Data
authors: Vehbi Comert, Hadi Yadavari, Mustafa Altun, and Ertunc Erturk
presented at: European Safety and Reliability Conference, Wroclaw ,Poland, 2014.

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Paper

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title: Warranty Forecasting of Electronic Boards using Short-term Field Data
authors: Vehbi Comert, Mustafa Altun, Mustafa Nadar, and Ertunc Erturk
accepted at: Reliability and Maintainability Symposium, Palm Harbor, FL, 2015.

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Abstract

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Slides

Funding Projects
title: A reliability Methodology for Appliance Electronic Cards
agency & program: TUBITAK University-Industry Collaboration Grant Program (1505)
duration: 2013-2015
title: Gate Oxide Breakdown Failure Mechanism of CMOS Transistors
agency & program: TUBITAK Industry Oriented Senior Project Support Program (2241/A)
duration: 2013-2014


Quantum Circuit Design

Synthesis and Optimization

We propose a fast synthesis algorithm that implements any given reversible Boolean function with quantum gates. Instead of an exhaustive search on every given function, our algorithm creates a library of essential functions and performs sorting. As an example, to implement 4 bit circuits we only use 120 essential functions out of all 20922789888000 functions.

By considering the physical structure of quantum gates, we show that optimum area solutions proposed in the literature are not actually optimum; they can be improved.

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Selected Publications
title: An Efficient Algorithm to Synthesize Quantum Circuits and Optimization
authors: Ömercan Susam and Mustafa Altun
submitted to: IEEE International Conference on Electronics Circuits and Systems,
Marseille, France, 2014.

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Paper

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Slides

Funding Projects
title: Quantum Circuit Design and Computation
agency & program: Istanbul Technical University Research Support Program (ITU-BAP)
duration: 2014-2015
title: Synthesizing Quantum Circuits
agency & program: TUBITAK MSc Scholarship Program in Priority Areas (2210/C)
duration: 2014-2015


Analog Circuit Design

Positive Feedback

The conventional wisdom is that analog circuits should not include positive feedback loops. As controversial as it seems, we have successfully used positive feedback for impedance improvement in a current amplifier. With adding few transistors we have achieved very low input resistance values. Additionally, we have proposed a new fully-differential current amplifier and tested it in a filter application.

Selected Publications
title: Design of a Fully Differential Current Mode Operational Amplifier with its Filter Applications
authors: Mustafa Altun and Hakan Kuntman
appeared in: AEU International Journal of Electronics and Communications,
Vol. 62, Issue 3, pp. 39–44, 2008.
presented at: ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa, Italy, 2007.

PDF.png
Paper

PPT.jpg
Slides


Discrete Mathematics

Self Duality Problem

The problem of testing whether a monotone Boolean function in irredundant disjuntive normal form (IDNF) is self-dual is one of few problems in circuit/time complexity whose precise tractability status is unknown. We have focused on this famous problem. We have shown that monotone self-dual Boolean functions in IDNF do not have more variables than disjuncts. We have proposed an algorithm to test whether a monotone Boolean function in IDNF with n variables and n disjuncts is self-dual. The algorithm runs in O(n^3) time.

Selected Publications
title: A Study on Monotone Self-dual Boolean Functions
authors: Mustafa Altun and Marc Riedel
submitted  to: ..., 2014.

PDF.png
Paper

PPT.jpg
Slides

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